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Paper Abstract and Keywords
Presentation 2018-02-20 16:10
Testing the Bridge Interconnect Fault for Memory based Reconfigurable Logic Device (MRLD)
Senling Wang, Tatsuya Ogawa, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Masayuki Sato, Mitsunori Katsu (TRL), Shoichi Sekiguchi (TAIYOYUDEN) DC2017-87
Abstract (in Japanese) (See Japanese page) 
(in English) MRLD is a promising alternative to FPGA with the benefits of low production cost, low power and small delay. In order to improve the yield and reliability of MRLD, in [6] we have developed the test approaches for detecting the interconnect faults including the stuck-at and bridge faults of MRLD. However, the test method for bridge faults of MRLD presented in [6] did not consider possible bridges between any interconnects in MRLD. Therefore, in this paper, we improve the test method of [6] for detecting the bridge faults between any interconnects that takes the Place-and-Route into account. The experimental results confirmed the effectiveness of the proposed test method.
Keyword (in Japanese) (See Japanese page) 
(in English) Reconfigurable Device / MRLD / FPGA / Reliability / Interconnect defects / Testing / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 444, DC2017-87, pp. 61-66, Feb. 2018.
Paper # DC2017-87 
Date of Issue 2018-02-13 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2018-02-20 - 2018-02-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc. 
Paper Information
Registration To DC 
Conference Code 2018-02-DC 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Testing the Bridge Interconnect Fault for Memory based Reconfigurable Logic Device (MRLD) 
Sub Title (in English)  
Keyword(1) Reconfigurable Device  
Keyword(2) MRLD  
Keyword(3) FPGA  
Keyword(4) Reliability  
Keyword(5) Interconnect defects  
Keyword(6) Testing  
Keyword(7)  
Keyword(8)  
1st Author's Name Senling Wang  
1st Author's Affiliation Ehime University (Ehime Univ.)
2nd Author's Name Tatsuya Ogawa  
2nd Author's Affiliation Ehime University (Ehime Univ.)
3rd Author's Name Yoshinobu Higami  
3rd Author's Affiliation Ehime University (Ehime Univ.)
4th Author's Name Hiroshi Takahashi  
4th Author's Affiliation Ehime University (Ehime Univ.)
5th Author's Name Masayuki Sato  
5th Author's Affiliation TRL Corp. (TRL)
6th Author's Name Mitsunori Katsu  
6th Author's Affiliation TRL Corp. (TRL)
7th Author's Name Shoichi Sekiguchi  
7th Author's Affiliation TAIYOYUDEN (TAIYOYUDEN)
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Speaker Author-1 
Date Time 2018-02-20 16:10:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2017-87 
Volume (vol) vol.117 
Number (no) no.444 
Page pp.61-66 
#Pages 6 
Date of Issue 2018-02-13 (DC) 

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