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Paper Abstract and Keywords
Presentation 2018-02-20 09:55
A Test Register Assignment Method for Operational Units to Reduce the Number of Test Patterns for Transition Faults Using Controller Augmentation
Yuki Takeuchi, Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2017-78
Abstract (in Japanese) (See Japanese page) 
(in English) It is required to reduce the number of test patterns to reduce test cost for VLSIs. Especially, design-for-testability methods at register transfer level are important to enhance the efficiency of dynamic test compaction. In this paper, we propose a test register assignment method for concurrent operational unit testing to reduce the number of test patterns for transition faults on at-speed scan testing, and use controller augmentation as our design-for-testability method to enable the concurrent testing. It is expected that the efficiency of dynamic test compaction becomes high since concurrent operational unit testing can be executed for circuits which controller augmentation is applied. Experimental results for high-level benchmark circuits show that the number of test patterns was reduced by 7.35% with 0.45% rea overhead on average.
Keyword (in Japanese) (See Japanese page) 
(in English) test register assignment / controller augmentation / invaild test states / test scheduling / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 444, DC2017-78, pp. 7-12, Feb. 2018.
Paper # DC2017-78 
Date of Issue 2018-02-13 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2018-02-20 - 2018-02-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc. 
Paper Information
Registration To DC 
Conference Code 2018-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Test Register Assignment Method for Operational Units to Reduce the Number of Test Patterns for Transition Faults Using Controller Augmentation 
Sub Title (in English)  
Keyword(1) test register assignment  
Keyword(2) controller augmentation  
Keyword(3) invaild test states  
Keyword(4) test scheduling  
1st Author's Name Yuki Takeuchi  
1st Author's Affiliation Nihon University (Nihon Univ.)
2nd Author's Name Shun Takeda  
2nd Author's Affiliation Nihon University (Nihon Univ.)
3rd Author's Name Toshinori Hosokawa  
3rd Author's Affiliation Nihon University (Nihon Univ.)
4th Author's Name Hiroshi Yamazaki  
4th Author's Affiliation Nihon University (Nihon Univ.)
5th Author's Name Masayoshi Yoshimura  
5th Author's Affiliation Kyoto Sangyo University (Kyoto Sangyo Univ.)
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Speaker Author-1 
Date Time 2018-02-20 09:55:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2017-78 
Volume (vol) vol.117 
Number (no) no.444 
Page pp.7-12 
Date of Issue 2018-02-13 (DC) 

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