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Paper Abstract and Keywords
Presentation 2018-02-28 17:45
Evaluation of Soft Error Tolerance on Flip-Flop depending on 65 nm FDSOI Transistor Threshold-Voltage
Mitsunori Ebara, Haruki Maruoka, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-104
Abstract (in Japanese) (See Japanese page) 
(in English) Moore's Law has been miniaturizing integrated circuits, which
can make a lot of high performance devices such as PCs and mobile
phones. However, reliability issues have become a significant concern due
to a soft error caused by radiation. The device can recover from the
soft error by restarting because the soft error is a
transient error. However, it is a serious problem especially
for several devices related to human life. Thus, the research of the soft error
is very important.

Leakage current is one of problems in the Internet of Things (IoT)
society in recent years. We evaluated a soft error tolerance of two
difference chips with low-power (LP) and low-standby-power (LSTP)
transistors respectively.
In 65 nm FDSOI process using Ar and
Kr ions. The measurement results show that the chip with LSTP transistors is 2X stronger against soft errors than
that with LP transistors.
Keyword (in Japanese) (See Japanese page) 
(in English) soft error / flip-flop / FDSOI / heavy ion / threshold voltage / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 455, VLD2017-104, pp. 91-96, Feb. 2018.
Paper # VLD2017-104 
Date of Issue 2018-02-21 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2017-104

Conference Information
Committee VLD HWS  
Conference Date 2018-02-28 - 2018-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2018-02-VLD-HWS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Evaluation of Soft Error Tolerance on Flip-Flop depending on 65 nm FDSOI Transistor Threshold-Voltage 
Sub Title (in English)  
Keyword(1) soft error  
Keyword(2) flip-flop  
Keyword(3) FDSOI  
Keyword(4) heavy ion  
Keyword(5) threshold voltage  
1st Author's Name Mitsunori Ebara  
1st Author's Affiliation Kyoto Institute of Technology (KIT)
2nd Author's Name Haruki Maruoka  
2nd Author's Affiliation Kyoto Institute of Technology (KIT)
3rd Author's Name Kodai Yamada  
3rd Author's Affiliation Kyoto Institute of Technology (KIT)
4th Author's Name Jun Furuta  
4th Author's Affiliation Kyoto Institute of Technology (KIT)
5th Author's Name Kazutoshi Kobayashi  
5th Author's Affiliation Kyoto Institute of Technology (KIT)
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Speaker Author-1 
Date Time 2018-02-28 17:45:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2017-104 
Volume (vol) vol.117 
Number (no) no.455 
Page pp.91-96 
Date of Issue 2018-02-21 (VLD) 

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