Paper Abstract and Keywords |
Presentation |
2018-02-28 13:55
Congestion Aware High Level Synthesis Design Flow with Source Compiler Masato Tatsuoka, Mineo Kaneko (JAIST) VLD2017-96 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
When we use a high level synthesis (HLS) tool, the optimization of input code is necessary for obtaining an optimized RTL. Especially routing congestion is difficult to resolve due to the lack of physical information in HLS phase. In conventional congestion aware high level design flows, routing congestion problems cannot be recognized before physically logic synthesis phase. When a routing congestion is found, it is necessary to modify the HLS input model written in SystemC or C/C++ in order to improve the RTL, and the repetition of improvement and correction of the HLS input model may degrade design productivity. In this paper, we propose a high-level design flow that performs code optimization by detecting the congested part on the high-level synthesis input model using the source code compiler. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
routing congestion / SystemC / Source Compiler / high level synthesis / RTL / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 455, VLD2017-96, pp. 43-48, Feb. 2018. |
Paper # |
VLD2017-96 |
Date of Issue |
2018-02-21 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2017-96 |
Conference Information |
Committee |
VLD HWS |
Conference Date |
2018-02-28 - 2018-03-02 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Seinen Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2018-02-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Congestion Aware High Level Synthesis Design Flow with Source Compiler |
Sub Title (in English) |
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routing congestion |
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SystemC |
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Source Compiler |
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high level synthesis |
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RTL |
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1st Author's Name |
Masato Tatsuoka |
1st Author's Affiliation |
Japan Advanced Institute of Science and Technology (JAIST) |
2nd Author's Name |
Mineo Kaneko |
2nd Author's Affiliation |
Japan Advanced Institute of Science and Technology (JAIST) |
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Speaker |
Author-1 |
Date Time |
2018-02-28 13:55:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2017-96 |
Volume (vol) |
vol.117 |
Number (no) |
no.455 |
Page |
pp.43-48 |
#Pages |
6 |
Date of Issue |
2018-02-21 (VLD) |
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