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Paper Abstract and Keywords
Presentation 2018-03-01 16:25
A Concept of DNN Framework for Embedded System Using FPGA
Ryota Yamamoto, Takuya Okamoto, Shinya Honda (Nagoya Univ.), Qian Zhao, Toki Matsumoto, Yukikazu Nakamoto (Hyogo Univ.), Tamotsu Sakai, Tetsuya Aoyama, Kazutoshi Wakabayashi (NEC) VLD2017-117
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, a DNN (Deep Neural Network) is used in many areas, and it required a field of an embedded system.
For an embedded systems, because its implementation may have severe restrictions on memory, speed, and real-time property.
On the other hand, an FPGA can be configured a flexible logic circuit for specializing calculations.
It can calculate faster than CPUs and lower power than GPUs.
This study, we consider a DNN framework for an embedded system using an FPGA.
Our framework has a generator for C language source code for high-level synthesis then configure FPGA using trained date generated by existent DNN framework.
This paper, we describe a concept of the framework and the relationship between our study and related work.
Keyword (in Japanese) (See Japanese page) 
(in English) Deep Learning / FPGA / High-Level Synthesis / / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 455, VLD2017-117, pp. 169-174, Feb. 2018.
Paper # VLD2017-117 
Date of Issue 2018-02-21 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2017-117

Conference Information
Committee VLD HWS  
Conference Date 2018-02-28 - 2018-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2018-02-VLD-HWS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Concept of DNN Framework for Embedded System Using FPGA 
Sub Title (in English)  
Keyword(1) Deep Learning  
Keyword(2) FPGA  
Keyword(3) High-Level Synthesis  
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1st Author's Name Ryota Yamamoto  
1st Author's Affiliation Nagoya University (Nagoya Univ.)
2nd Author's Name Takuya Okamoto  
2nd Author's Affiliation Nagoya University (Nagoya Univ.)
3rd Author's Name Shinya Honda  
3rd Author's Affiliation Nagoya University (Nagoya Univ.)
4th Author's Name Qian Zhao  
4th Author's Affiliation University of Hyogo (Hyogo Univ.)
5th Author's Name Toki Matsumoto  
5th Author's Affiliation University of Hyogo (Hyogo Univ.)
6th Author's Name Yukikazu Nakamoto  
6th Author's Affiliation University of Hyogo (Hyogo Univ.)
7th Author's Name Tamotsu Sakai  
7th Author's Affiliation NEC Corporation Inc. (NEC)
8th Author's Name Tetsuya Aoyama  
8th Author's Affiliation NEC Corporation Inc. (NEC)
9th Author's Name Kazutoshi Wakabayashi  
9th Author's Affiliation NEC Corporation Inc. (NEC)
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Speaker Author-1 
Date Time 2018-03-01 16:25:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2017-117 
Volume (vol) vol.117 
Number (no) no.455 
Page pp.169-174 
#Pages 6 
Date of Issue 2018-02-21 (VLD) 

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