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Paper Abstract and Keywords
Presentation 2018-03-07 16:10
Optimization of Memory Accesses of Large Scale Graph Analysis Using Multiport and Multibank Memory
Keigo Teramoto, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univ.) CPSY2017-136 DC2017-92
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, large scale graph analysis is getting important in the development of the Web and social networks. And in the benchmark tests such as the graph500 which evaluates the performance of large scale graph analysis, higher memory access bandwidth is required to achieve high performance. In response to such requirement, HMC (Hybrid Memory Cube) which is a three-dimensional memory provides high memory bandwidth with multiport and multibank access. In this paper, we designed a breadth-first search hardware that optimized memory access for the HMC-FPGA system. This implementation on FPGA achieved 21.9 MTEPS in performance.
Keyword (in Japanese) (See Japanese page) 
(in English) 3D memory / HMC / FPGA / Memory access / Breadth-first search / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 479, CPSY2017-136, pp. 101-106, March 2018.
Paper # CPSY2017-136 
Date of Issue 2018-02-28 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2017-136 DC2017-92

Conference Information
Committee CPSY DC IPSJ-SLDM IPSJ-EMB IPSJ-ARC  
Conference Date 2018-03-07 - 2018-03-08 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinoshima Bunka-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) ETNET2018 
Paper Information
Registration To CPSY 
Conference Code 2018-03-CPSY-DC-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Optimization of Memory Accesses of Large Scale Graph Analysis Using Multiport and Multibank Memory 
Sub Title (in English)  
Keyword(1) 3D memory  
Keyword(2) HMC  
Keyword(3) FPGA  
Keyword(4) Memory access  
Keyword(5) Breadth-first search  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Keigo Teramoto  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Atsushi Kubota  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Tetsuo Hironaka  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
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Speaker Author-1 
Date Time 2018-03-07 16:10:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2017-136, DC2017-92 
Volume (vol) vol.117 
Number (no) no.479(CPSY), no.480(DC) 
Page pp.101-106 
#Pages 6 
Date of Issue 2018-02-28 (CPSY, DC) 

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