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Paper Abstract and Keywords
Presentation 2018-08-08 13:15
[Invited Lecture] A Highly Symmetrical 10T 2-Read/Write Dual-port SRAM Bitcell Design In 28nm High-k/Metal-gate Planar Bulk CMOS Technology
Yuichiro Ishii, Miki Tanaka, Makoto Yabuuchi, Yohei Sawada, Shinji Tanaka, Koji Nii (Renesas), Tien Yu Lu, Chun Hsien Huang, Shou Sian Chen, Yu Tse Kuo, Ching Cheng Lung, Osbert Cheng (UMC) SDM2018-40 ICD2018-27
Abstract (in Japanese) (See Japanese page) 
(in English) We propose a highly symmetrical 10T 2-read/write (2RW) dual-port (DP) SRAM bitcell in 28-nm high-k/metal-gate planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (Iread) and SNM are respectively boosted by +20% and +15 mV by introducing proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) NMOSs. Measured Vmin of proposed 256-kbit 10T DP SRAM is 0.53 V at TT process, 25°C under the worst access condition with read/write disturbances, improved by 90 mV (15%) compared to the conventional one.
Keyword (in Japanese) (See Japanese page) 
(in English) SRAM / Dual Port / bitcell / 8T / 10T / read disturbance / write disturbance /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 173, ICD2018-27, pp. 83-88, Aug. 2018.
Paper # ICD2018-27 
Date of Issue 2018-07-31 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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Download PDF SDM2018-40 ICD2018-27

Conference Information
Committee SDM ICD ITE-IST  
Conference Date 2018-08-07 - 2018-08-09 
Place (in Japanese) (See Japanese page) 
Place (in English) Hokkaido Univ., Graduate School of IST M Bldg., M151 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications 
Paper Information
Registration To ICD 
Conference Code 2018-08-SDM-ICD-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Highly Symmetrical 10T 2-Read/Write Dual-port SRAM Bitcell Design In 28nm High-k/Metal-gate Planar Bulk CMOS Technology 
Sub Title (in English)  
Keyword(1) SRAM  
Keyword(2) Dual Port  
Keyword(3) bitcell  
Keyword(4) 8T  
Keyword(5) 10T  
Keyword(6) read disturbance  
Keyword(7) write disturbance  
Keyword(8)  
1st Author's Name Yuichiro Ishii  
1st Author's Affiliation Renesas Electronics (Renesas)
2nd Author's Name Miki Tanaka  
2nd Author's Affiliation Renesas Electronics (Renesas)
3rd Author's Name Makoto Yabuuchi  
3rd Author's Affiliation Renesas Electronics (Renesas)
4th Author's Name Yohei Sawada  
4th Author's Affiliation Renesas Electronics (Renesas)
5th Author's Name Shinji Tanaka  
5th Author's Affiliation Renesas Electronics (Renesas)
6th Author's Name Koji Nii  
6th Author's Affiliation Renesas Electronics (Renesas)
7th Author's Name Tien Yu Lu  
7th Author's Affiliation United Microelectronics Corporation (UMC)
8th Author's Name Chun Hsien Huang  
8th Author's Affiliation United Microelectronics Corporation (UMC)
9th Author's Name Shou Sian Chen  
9th Author's Affiliation United Microelectronics Corporation (UMC)
10th Author's Name Yu Tse Kuo  
10th Author's Affiliation United Microelectronics Corporation (UMC)
11th Author's Name Ching Cheng Lung  
11th Author's Affiliation United Microelectronics Corporation (UMC)
12th Author's Name Osbert Cheng  
12th Author's Affiliation United Microelectronics Corporation (UMC)
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Speaker Author-1 
Date Time 2018-08-08 13:15:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # SDM2018-40, ICD2018-27 
Volume (vol) vol.118 
Number (no) no.172(SDM), no.173(ICD) 
Page pp.83-88 
#Pages
Date of Issue 2018-07-31 (SDM, ICD) 


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