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Paper Abstract and Keywords
Presentation 2018-09-18 14:50
Data Flow Representation and its Applications to Machine Learning Accelerator
Kazuki Nakada (Tsukuba Univ. of Tech.), Keiji Miura (Kwansei Gakuin Univ.) RECONF2018-32
Abstract (in Japanese) (See Japanese page) 
(in English) Researches and development of machine learning accelerators have been rapidly progressing. It is becoming important to represent machine learning algorithms as data flow graph and to embed data flow structure on hardware platforms as an approach to efficiently design machine learning accelerators. In this study, we present to implement hardware accelerators for (i) Topological Data Analysis and (ii) Reinforcement Learning by focusing on their data flow representation. First, we briefly review the previous works on data flow representation of machine learning algorithms
and their hardware implementation. Second, as a case study, we represent each algorithm of Topological Data Analysis and Reinforcement Learning
as a data flow graph, and their hardware implementation based on the data flow graph. Finally, we show that machine learning accelerators can be efficiently designed by using MATLAB/Simulink and HDL Coder, which is a tool that graphically expresses data flow and generates HDL according to computation of various degrees of abstraction.
Keyword (in Japanese) (See Japanese page) 
(in English) Machine Learning / Hardware Accelerator / Data Flow Graph / Field-Programmable Gate Array (FPGA) / Hardware Description Language / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 215, RECONF2018-32, pp. 73-78, Sept. 2018.
Paper # RECONF2018-32 
Date of Issue 2018-09-10 (RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Notes on Review This article is a technical report without peer review, and its polished version will be published elsewhere.
Download PDF RECONF2018-32

Conference Information
Committee RECONF  
Conference Date 2018-09-17 - 2018-09-18 
Place (in Japanese) (See Japanese page) 
Place (in English) LINE Fukuoka Cafe Space 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2018-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Data Flow Representation and its Applications to Machine Learning Accelerator 
Sub Title (in English)  
Keyword(1) Machine Learning  
Keyword(2) Hardware Accelerator  
Keyword(3) Data Flow Graph  
Keyword(4) Field-Programmable Gate Array (FPGA)  
Keyword(5) Hardware Description Language  
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Keyword(7)  
Keyword(8)  
1st Author's Name Kazuki Nakada  
1st Author's Affiliation Tsukuba University of Technology (Tsukuba Univ. of Tech.)
2nd Author's Name Keiji Miura  
2nd Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
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Speaker Author-1 
Date Time 2018-09-18 14:50:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2018-32 
Volume (vol) vol.118 
Number (no) no.215 
Page pp.73-78 
#Pages 6 
Date of Issue 2018-09-10 (RECONF) 

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