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Paper Abstract and Keywords
Presentation 2018-10-29 14:30
An Acceleration of Compressed Squaring for Pairing Implementation with Pipeline Modular Multiplier
Yota Okuaki, Junichi Sakamoto, Naoki Yoshida, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) HWS2018-50 ICD2018-42 Link to ES Tech. Rep. Archives: ICD2018-42
Abstract (in Japanese) (See Japanese page) 
(in English) One of the biggest problems of the emerging cyber-physical and cloud computing systems is how to ensure security with energy efficiency. As a solution to the problem there is a growing expectation of adopting advanced cryptography with rich functionalities such as searchable encryption which enables direct data retrieval over encrypted database without decrypting the database, and so on. Most of advanced cryptography use a pairing calculation as a component. It is required that we speed up a pairing calculation for the spread of advanced cryptography. In this paper, we describe how the record latency 91.2 µs on FPGA board KCU105 for calculation of Optimal Ate pairing over BN curve on 254 bit prime field was achieved. The pairing calculator uses pipeline modular multipliers with improved scheduling for compressed squaring, reduced number of clock cycles on Miller Loop and Final Addition, and higher maximum operating frequency.
Keyword (in Japanese) (See Japanese page) 
(in English) Hardware Security / Pairing Encryption / FPGA Implementation / Pipeline Implementation / Compressed Squaring / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 272, HWS2018-50, pp. 19-24, Oct. 2018.
Paper # HWS2018-50 
Date of Issue 2018-10-22 (HWS, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF HWS2018-50 ICD2018-42 Link to ES Tech. Rep. Archives: ICD2018-42

Conference Information
Committee HWS ICD  
Conference Date 2018-10-29 - 2018-10-29 
Place (in Japanese) (See Japanese page) 
Place (in English) Kobe Univ. Umeda Intelligent Laboratory 
Topics (in Japanese) (See Japanese page) 
Topics (in English) HardwareSecurity, etc. 
Paper Information
Registration To HWS 
Conference Code 2018-10-HWS-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Acceleration of Compressed Squaring for Pairing Implementation with Pipeline Modular Multiplier 
Sub Title (in English)  
Keyword(1) Hardware Security  
Keyword(2) Pairing Encryption  
Keyword(3) FPGA Implementation  
Keyword(4) Pipeline Implementation  
Keyword(5) Compressed Squaring  
1st Author's Name Yota Okuaki  
1st Author's Affiliation Yokohama National University (YNU)
2nd Author's Name Junichi Sakamoto  
2nd Author's Affiliation Yokohama National University (YNU)
3rd Author's Name Naoki Yoshida  
3rd Author's Affiliation Yokohama National University (YNU)
4th Author's Name Daisuke Fujimoto  
4th Author's Affiliation Yokohama National University (YNU)
5th Author's Name Tsutomu Matsumoto  
5th Author's Affiliation Yokohama National University (YNU)
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Speaker Author-1 
Date Time 2018-10-29 14:30:00 
Presentation Time 25 minutes 
Registration for HWS 
Paper # HWS2018-50, ICD2018-42 
Volume (vol) vol.118 
Number (no) no.272(HWS), no.273(ICD) 
Page pp.19-24 
Date of Issue 2018-10-22 (HWS, ICD) 

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