Paper Abstract and Keywords |
Presentation |
2018-12-06 09:25
Quality determination of logic element placement using deep learning in fine grain reconfigurable device MPLD Hidehito Fujiishi, Tokio Kamada, Tetsuo Hironaka, Kazuya Tanigawa, Atsushi Kubota (Hiroshima city Univ.) VLD2018-48 DC2018-34 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In CAD for MPLD which is a type of fine grain reconfigurable PLD, the SA method is used as a place-ment method for logic elements. However, since the wiring structure of the MPLD is complicated, it is difficult to implement the cost function for the SA method as a simple mathematical model.
Therefore, we considered implementing the cost function for the SA method with a neural network.
In this paper, in order to ascertain whether a neural network that predicts the ease of wiring can be trained, we trained the
neural network using the values from the conventional MPLD’s SA cost
function as pseudo learning data. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
MPLD / Placement and Route / SA(Simulated Annealing) / Neural Network / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 118, no. 334, VLD2018-48, pp. 71-76, Dec. 2018. |
Paper # |
VLD2018-48 |
Date of Issue |
2018-11-28 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2018-48 DC2018-34 |
Conference Information |
Committee |
VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM |
Conference Date |
2018-12-05 - 2018-12-07 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Satellite Campus Hiroshima |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2018 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2018-12-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Quality determination of logic element placement using deep learning in fine grain reconfigurable device MPLD |
Sub Title (in English) |
|
Keyword(1) |
MPLD |
Keyword(2) |
Placement and Route |
Keyword(3) |
SA(Simulated Annealing) |
Keyword(4) |
Neural Network |
Keyword(5) |
|
Keyword(6) |
|
Keyword(7) |
|
Keyword(8) |
|
1st Author's Name |
Hidehito Fujiishi |
1st Author's Affiliation |
Hiroshima city University (Hiroshima city Univ.) |
2nd Author's Name |
Tokio Kamada |
2nd Author's Affiliation |
Hiroshima city University (Hiroshima city Univ.) |
3rd Author's Name |
Tetsuo Hironaka |
3rd Author's Affiliation |
Hiroshima city University (Hiroshima city Univ.) |
4th Author's Name |
Kazuya Tanigawa |
4th Author's Affiliation |
Hiroshima city University (Hiroshima city Univ.) |
5th Author's Name |
Atsushi Kubota |
5th Author's Affiliation |
Hiroshima city University (Hiroshima city Univ.) |
6th Author's Name |
|
6th Author's Affiliation |
() |
7th Author's Name |
|
7th Author's Affiliation |
() |
8th Author's Name |
|
8th Author's Affiliation |
() |
9th Author's Name |
|
9th Author's Affiliation |
() |
10th Author's Name |
|
10th Author's Affiliation |
() |
11th Author's Name |
|
11th Author's Affiliation |
() |
12th Author's Name |
|
12th Author's Affiliation |
() |
13th Author's Name |
|
13th Author's Affiliation |
() |
14th Author's Name |
|
14th Author's Affiliation |
() |
15th Author's Name |
|
15th Author's Affiliation |
() |
16th Author's Name |
|
16th Author's Affiliation |
() |
17th Author's Name |
|
17th Author's Affiliation |
() |
18th Author's Name |
|
18th Author's Affiliation |
() |
19th Author's Name |
|
19th Author's Affiliation |
() |
20th Author's Name |
|
20th Author's Affiliation |
() |
Speaker |
Author-1 |
Date Time |
2018-12-06 09:25:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2018-48, DC2018-34 |
Volume (vol) |
vol.118 |
Number (no) |
no.334(VLD), no.335(DC) |
Page |
pp.71-76 |
#Pages |
6 |
Date of Issue |
2018-11-28 (VLD, DC) |
|