Paper Abstract and Keywords |
Presentation |
2018-12-06 13:25
Evaluation of Flexible Test Power Control for Logic BIST in TEG Chips Takaaki Kato (KIT), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (KIT) VLD2018-57 DC2018-43 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Scan-based logic BIST has a crucial problem of high test power dissipation. Its solution requires a flexible test power control specified for each circuit because of trade-off between test power, fault coverage, and test application time. This paper addresses evaluation of the scan-in power reduction techniques with scan-out and capture reduction techniques. In addition to simulation-based experiments, measurement results of TEG chips’ experiments are shown to make sure the effectiveness of the techniques. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
BIST / Scan Test / Scan power / Capture power / Multi-Cycle Test / / / |
Reference Info. |
IEICE Tech. Rep., vol. 118, no. 335, DC2018-43, pp. 125-130, Dec. 2018. |
Paper # |
DC2018-43 |
Date of Issue |
2018-11-28 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2018-57 DC2018-43 |
Conference Information |
Committee |
VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM |
Conference Date |
2018-12-05 - 2018-12-07 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Satellite Campus Hiroshima |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2018 -New Field of VLSI Design- |
Paper Information |
Registration To |
DC |
Conference Code |
2018-12-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Evaluation of Flexible Test Power Control for Logic BIST in TEG Chips |
Sub Title (in English) |
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Keyword(1) |
BIST |
Keyword(2) |
Scan Test |
Keyword(3) |
Scan power |
Keyword(4) |
Capture power |
Keyword(5) |
Multi-Cycle Test |
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Keyword(7) |
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1st Author's Name |
Takaaki Kato |
1st Author's Affiliation |
Kyushu Institute of Technology (KIT) |
2nd Author's Name |
Senling Wang |
2nd Author's Affiliation |
Ehime University (Ehime Univ.) |
3rd Author's Name |
Yasuo Sato |
3rd Author's Affiliation |
Kyushu Institute of Technology (KIT) |
4th Author's Name |
Seiji Kajihara |
4th Author's Affiliation |
Kyushu Institute of Technology (KIT) |
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Speaker |
Author-1 |
Date Time |
2018-12-06 13:25:00 |
Presentation Time |
25 minutes |
Registration for |
DC |
Paper # |
VLD2018-57, DC2018-43 |
Volume (vol) |
vol.118 |
Number (no) |
no.334(VLD), no.335(DC) |
Page |
pp.125-130 |
#Pages |
6 |
Date of Issue |
2018-11-28 (VLD, DC) |
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