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Paper Abstract and Keywords
Presentation 2018-12-06 13:00
Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-56 DC2018-42
Abstract (in Japanese) (See Japanese page) 
(in English) 3D die-stacking technique using TSVs has gained much attention as a new integration method of IC.
However, faulty TSVs may cause small delay faults because of defects in TSVs such as voids and pinholes during the manufacturing process.
We have been proposed a DFT(Design-For-Testability) method for TSVs using a boundary scan circuit with embedded TDC(TDCBS).
The TDCBS has a circuit component called delay line that has two roles.
One is to observe a delay in TSVs and the other is to apply a transition signal to TSV.
In this paper, we present a design to separate the delay lines into two parts for delay observation and for transition signal application in order to reduce test application time on TDCBS.
The proposed design can reduce test application time since the length of the scan chain is shortened by separating the delay lines.
Keyword (in Japanese) (See Japanese page) 
(in English) small delay fault / TSV / TDC / boundary scan / Design-For-Testability / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 335, DC2018-42, pp. 119-124, Dec. 2018.
Paper # DC2018-42 
Date of Issue 2018-11-28 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2018-56 DC2018-42

Conference Information
Committee VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM 
Conference Date 2018-12-05 - 2018-12-07 
Place (in Japanese) (See Japanese page) 
Place (in English) Satellite Campus Hiroshima 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2018 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2018-12-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC 
Sub Title (in English)  
Keyword(1) small delay fault  
Keyword(2) TSV  
Keyword(3) TDC  
Keyword(4) boundary scan  
Keyword(5) Design-For-Testability  
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Keyword(7)  
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1st Author's Name Satoshi Hirai  
1st Author's Affiliation Tokushima University (Tokushima Univ.)
2nd Author's Name Hiroyuki Yotsuyanagi  
2nd Author's Affiliation Tokushima University (Tokushima Univ.)
3rd Author's Name Masaki Hashizume  
3rd Author's Affiliation Tokushima University (Tokushima Univ.)
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Speaker Author-1 
Date Time 2018-12-06 13:00:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2018-56, DC2018-42 
Volume (vol) vol.118 
Number (no) no.334(VLD), no.335(DC) 
Page pp.119-124 
#Pages 6 
Date of Issue 2018-11-28 (VLD, DC) 

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