講演抄録/キーワード |
講演名 |
2018-12-06 09:00
Resources Utilization of Fine-grained Overlay Architecture ○Theingi Myint(Kumamoto)・Qian Zhao(Kyutech)・Motoki Amagasaki・Masahiro Iida・Toshinori Sueyoshi(Kumamoto) RECONF2018-37 |
抄録 |
(和) |
(まだ登録されていません) |
(英) |
This paper focuses on utilization of hardware resources for fine-grained overlay architecture. Overlay architectures include a regular arrangement of Reconfigurable Elements (REs) with routing channels interconnection. REs are composed of Logic Blocks (LBs) that are fine-grain reconfigurable elements. This paper emphasizes on the use of LUT structure and SLM structure for hardware resources that can be implemented on Field Programmable Gate Array (FPGA) device. In our CAD tool, we use ABC for mapping, VPR 7.0 in placement and EasyRouter in routing. After routing part, we get Hardware Description Language (HDL) and successful channel width. By using minimum channel width, we run in routing part again (re-routing). Then, we get HDL. According to this HDL results, the utilization resources of SLM structure are less than LUT structure on Xilinx Atrix-7 xc7a200tffg1156-1. |
キーワード |
(和) |
/ / / / / / / |
(英) |
fine-grained overlay / utilization resources / Reconfigurable Elements (REs) / HDL / / / / |
文献情報 |
信学技報, vol. 118, no. 340, RECONF2018-37, pp. 15-20, 2018年12月. |
資料番号 |
RECONF2018-37 |
発行日 |
2018-11-28 (RECONF) |
ISSN |
Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
RECONF2018-37 |