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| Paper Abstract and Keywords | ||
| Presentation | 2018-12-06 09:00 Resources Utilization of Fine-grained Overlay Architecture Theingi Myint (Kumamoto), Qian Zhao (Kyutech), Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto)  RECONF2018-37 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper focuses on utilization of hardware resources for fine-grained overlay architecture. Overlay architectures include a regular arrangement of Reconfigurable Elements (REs) with routing channels interconnection. REs are composed of Logic Blocks (LBs) that are fine-grain reconfigurable elements. This paper emphasizes on the use of LUT structure and SLM structure for hardware resources that can be implemented on Field Programmable Gate Array (FPGA) device. In our CAD tool, we use ABC for mapping, VPR 7.0 in placement and EasyRouter in routing. After routing part, we get Hardware Description Language (HDL) and successful channel width. By using minimum channel width, we run in routing part again (re-routing). Then, we get HDL. According to this HDL results, the utilization resources of SLM structure are less than LUT structure on Xilinx Atrix-7 xc7a200tffg1156-1. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | fine-grained overlay / utilization resources / Reconfigurable Elements (REs) / HDL / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 118, no. 340, RECONF2018-37, pp. 15-20, Dec. 2018. | |
| Paper # | RECONF2018-37 | |
| Date of Issue | 2018-11-28 (RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2018-37 |
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| Conference Information | |
| Committee | VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM |
| Conference Date | 2018-12-05 - 2018-12-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Satellite Campus Hiroshima |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2018 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2018-12-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Resources Utilization of Fine-grained Overlay Architecture |
| Sub Title (in English) | |
| Keyword(1) | fine-grained overlay |
| Keyword(2) | utilization resources |
| Keyword(3) | Reconfigurable Elements (REs) |
| Keyword(4) | HDL |
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| 1st Author's Name | Theingi Myint |
| 1st Author's Affiliation | Kumamoto University (Kumamoto) |
| 2nd Author's Name | Qian Zhao |
| 2nd Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 3rd Author's Name | Motoki Amagasaki |
| 3rd Author's Affiliation | Kumamoto University (Kumamoto) |
| 4th Author's Name | Masahiro Iida |
| 4th Author's Affiliation | Kumamoto University (Kumamoto) |
| 5th Author's Name | Toshinori Sueyoshi |
| 5th Author's Affiliation | Kumamoto University (Kumamoto) |
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| Speaker | Author-1 |
| Date Time | 2018-12-06 09:00:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2018-37 |
| Volume (vol) | vol.118 |
| Number (no) | no.340 |
| Page | pp.15-20 |
| #Pages | 6 |
| Date of Issue | 2018-11-28 (RECONF) |
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