Paper Abstract and Keywords |
Presentation |
2018-12-07 15:15
Real Chip Implementation of a verification scheme for an Inductive-Coupling ThruChip Interface Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Hideharu Amano (Keio Univ.) CPSY2018-42 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A building block computing system is one of the promising 3D Stacked VLSIs. It adopts an inductive coupling ThruChip Interface (TCI) for chip to chip interconnections, which can simultaneously realize flexible 3D stacking and low-cost fabrication. However, the TCIs have to be appropriately biased for proper communications. Thus, an efficient mean to find such bias points is required. In order to achieve this goal, we propose a verication scheme for the TCI so as to easily monitor the TCI functions. We disclose preliminary simulation results of the proposed scheme implemented with the SOTB 65-nm technology. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Building block computing system / ThruChip Interface / 3-D stacked VLSIs / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 118, no. 339, CPSY2018-42, pp. 53-58, Dec. 2018. |
Paper # |
CPSY2018-42 |
Date of Issue |
2018-11-28 (CPSY) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CPSY2018-42 |
Conference Information |
Committee |
VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM |
Conference Date |
2018-12-05 - 2018-12-07 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Satellite Campus Hiroshima |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2018 -New Field of VLSI Design- |
Paper Information |
Registration To |
CPSY |
Conference Code |
2018-12-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Real Chip Implementation of a verification scheme for an Inductive-Coupling ThruChip Interface |
Sub Title (in English) |
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Keyword(1) |
Building block computing system |
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ThruChip Interface |
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3-D stacked VLSIs |
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1st Author's Name |
Hideto Kayashima |
1st Author's Affiliation |
Keio University (Keio Univ.) |
2nd Author's Name |
Takuya Kojima |
2nd Author's Affiliation |
Keio University (Keio Univ.) |
3rd Author's Name |
Hayate Okuhara |
3rd Author's Affiliation |
Keio University (Keio Univ.) |
4th Author's Name |
Hideharu Amano |
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Keio University (Keio Univ.) |
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Speaker |
Author-1 |
Date Time |
2018-12-07 15:15:00 |
Presentation Time |
25 minutes |
Registration for |
CPSY |
Paper # |
CPSY2018-42 |
Volume (vol) |
vol.118 |
Number (no) |
no.339 |
Page |
pp.53-58 |
#Pages |
6 |
Date of Issue |
2018-11-28 (CPSY) |