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Paper Abstract and Keywords
Presentation 2018-12-07 14:35
Analysis of Conductive Power Noise Characteristics in Digital IC Chips between two Different IC Packaging Structures
Akihiro Tsukioka, Kosuke Jike, Koh Watanabe, Noriyuki Miura, Makoto Nagata (Kobe Univ.) CPM2018-96 ICD2018-57 IE2018-75 Link to ES Tech. Rep. Archives: CPM2018-96 ICD2018-57
Abstract (in Japanese) (See Japanese page) 
(in English) The conducted and radiated emission are caused by the dynamic power consumption in digital circuit operations. The characteristics of those emissions are associated to the power delivery network impedance for the electrical system. The package style has an impact on the power noise profiles. This paper describes and evaluates a simulation techniques for representing the on chip power noise for two IC packaging structures.
Keyword (in Japanese) (See Japanese page) 
(in English) Dynamic power noise / Integrated circuit packaging / Electromagnetic interference / On chip monitor / Chip power model / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 337, ICD2018-57, pp. 37-42, Dec. 2018.
Paper # ICD2018-57 
Date of Issue 2018-11-28 (CPM, ICD, IE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPM2018-96 ICD2018-57 IE2018-75 Link to ES Tech. Rep. Archives: CPM2018-96 ICD2018-57

Conference Information
Committee VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM 
Conference Date 2018-12-05 - 2018-12-07 
Place (in Japanese) (See Japanese page) 
Place (in English) Satellite Campus Hiroshima 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2018 -New Field of VLSI Design- 
Paper Information
Registration To ICD 
Conference Code 2018-12-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Analysis of Conductive Power Noise Characteristics in Digital IC Chips between two Different IC Packaging Structures 
Sub Title (in English)  
Keyword(1) Dynamic power noise  
Keyword(2) Integrated circuit packaging  
Keyword(3) Electromagnetic interference  
Keyword(4) On chip monitor  
Keyword(5) Chip power model  
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Keyword(7)  
Keyword(8)  
1st Author's Name Akihiro Tsukioka  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name Kosuke Jike  
2nd Author's Affiliation Kobe University (Kobe Univ.)
3rd Author's Name Koh Watanabe  
3rd Author's Affiliation Kobe University (Kobe Univ.)
4th Author's Name Noriyuki Miura  
4th Author's Affiliation Kobe University (Kobe Univ.)
5th Author's Name Makoto Nagata  
5th Author's Affiliation Kobe University (Kobe Univ.)
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Speaker Author-1 
Date Time 2018-12-07 14:35:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # CPM2018-96, ICD2018-57, IE2018-75 
Volume (vol) vol.118 
Number (no) no.336(CPM), no.337(ICD), no.338(IE) 
Page pp.37-42 
#Pages
Date of Issue 2018-11-28 (CPM, ICD, IE) 


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