Paper Abstract and Keywords |
Presentation |
2019-02-27 13:05
Wire Load Model for Power Consumption Evaluation of Via-Switch FPGA Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2018-97 HWS2018-60 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this report, we consider a wire load model for an FPGA using new nano-device called via-switch to allow power estimation before placement and routing of application circuits.
We evaluate the accuracy of the proposed model by comparing the power estimation by circuit simulation using the switch count that is estimated by the proposed model and those from the post-placement-and-routing layout information.
Using the proposed model, the maximum and minimum estimation error is $−8.2$% and $−2.7$%, respectively. This report also discusses the estimation accuracy of power consumption with the proposed model by comparing the values estimated by the proposed model and HSPICE simulation. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
atom switch / reconfigurable architecture / power estimation / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 118, no. 457, VLD2018-97, pp. 25-30, Feb. 2019. |
Paper # |
VLD2018-97 |
Date of Issue |
2019-02-20 (VLD, HWS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2018-97 HWS2018-60 |
Conference Information |
Committee |
HWS VLD |
Conference Date |
2019-02-27 - 2019-03-02 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Ken Seinen Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Technology for System-on-Silicon, Hardware Security, etc. |
Paper Information |
Registration To |
VLD |
Conference Code |
2019-02-HWS-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Wire Load Model for Power Consumption Evaluation of Via-Switch FPGA |
Sub Title (in English) |
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Keyword(1) |
atom switch |
Keyword(2) |
reconfigurable architecture |
Keyword(3) |
power estimation |
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1st Author's Name |
Asuka Natsuhara |
1st Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
2nd Author's Name |
Takashi Imagawa |
2nd Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
3rd Author's Name |
Hiroyuki Ochi |
3rd Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
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Speaker |
Author-1 |
Date Time |
2019-02-27 13:05:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2018-97, HWS2018-60 |
Volume (vol) |
vol.118 |
Number (no) |
no.457(VLD), no.458(HWS) |
Page |
pp.25-30 |
#Pages |
6 |
Date of Issue |
2019-02-20 (VLD, HWS) |
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