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Paper Abstract and Keywords
Presentation 2019-02-27 15:35
Improvement of Flip-Flop Performance Considering the Influence of Power Supply Noise
Yuya Kinoshita, Yukiya Miura (Tokyo Metropolitan Univ.) DC2018-82
Abstract (in Japanese) (See Japanese page) 
(in English) With the scaling down and low-power operation of VLSI circuits, influence on circuit behavior by power supply noise such as IR-drop becomes noticeable. Error occurrence on SRAMs by power supply noise and several countermeasures have already been reported. On the other hand, similar study for FF (Flip-Flop) circuits that are one of memory elements is not popular than SRAMs. In our previous study, several new FF circuits which are countermeasures for errors have been developed. FFs of a transmission gate type had been showed good performance for power supply noise. However, effectiveness of a clocked inverter type for noise was small. In this study, we consider the cause of the low effectiveness for clocked inverter FFs and propose its improvement method. We verify the effectiveness for power supply noise of improved FFs and evaluate circuit performance by using circuit simulation.
Keyword (in Japanese) (See Japanese page) 
(in English) Power Supply Noise / Flip-Flop / Error / Bit-Flip / Clocked Inverter / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 456, DC2018-82, pp. 67-72, Feb. 2019.
Paper # DC2018-82 
Date of Issue 2019-02-20 (DC) 
ISSN Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2019-02-27 - 2019-02-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc. 
Paper Information
Registration To DC 
Conference Code 2019-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Improvement of Flip-Flop Performance Considering the Influence of Power Supply Noise 
Sub Title (in English)  
Keyword(1) Power Supply Noise  
Keyword(2) Flip-Flop  
Keyword(3) Error  
Keyword(4) Bit-Flip  
Keyword(5) Clocked Inverter  
1st Author's Name Yuya Kinoshita  
1st Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
2nd Author's Name Yukiya Miura  
2nd Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
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Speaker Author-1 
Date Time 2019-02-27 15:35:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2018-82 
Volume (vol) vol.118 
Number (no) no.456 
Page pp.67-72 
Date of Issue 2019-02-20 (DC) 

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