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| Presentation | 2019-02-28 13:05 High-Speed and Noise-Tolerant High-Radix Tree Domino Adder Targeted to 65 nm FD-SOI Technology Kazuki Niino, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.)  VLD2018-112 HWS2018-75 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Domino logic was introduced at the forefront of the LSI market in the 2000s for high-speed circuits. In recent years, however, domino logic has been rarely introduced due to the unreliability factors such as large dynamic power and exponential increase of leakage current induced by the progress of fabrication technology. On the other hand, siliconon thin buried oxide (SOTB) has attracted attention as a new CMOS process technology. SOTB is a type of fully depleted silicon-on-insulator (FD-SOI), and its parasitic capacitance and leakage current are small due to its structure. In this report, we propose a high-radix tree adder that exploits these features of SOTB. To improve the performance of the proposed adder, we explore an appropriate transistor sizing based on the analysis of unreliability factors. The evaluation result shows that the delay of the proposed 23-bit, 64-bit high-radix tree adders are 3.2% and 1.8% smaller than that of the radix-2 tree adder, respectively. Moreover, by comparison with bulk CMOS, it showed high affinity of SOTB and domino logic. The 16-bit multiplier with the proposed adders shows 27.4% to 34.3% smaller delay than that of the standard-cell-based static CMOS designed by Synopsys Design Compiler. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | domino logic / SOTB / leakage current / keeper / multiplier / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 118, no. 457, VLD2018-112, pp. 115-120, Feb. 2019. | |
| Paper # | VLD2018-112 | |
| Date of Issue | 2019-02-20 (VLD, HWS) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2018-112 HWS2018-75 |
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| Conference Information | |
| Committee | HWS VLD |
| Conference Date | 2019-02-27 - 2019-03-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2019-02-HWS-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High-Speed and Noise-Tolerant High-Radix Tree Domino Adder Targeted to 65 nm FD-SOI Technology |
| Sub Title (in English) | |
| Keyword(1) | domino logic |
| Keyword(2) | SOTB |
| Keyword(3) | leakage current |
| Keyword(4) | keeper |
| Keyword(5) | multiplier |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kazuki Niino |
| 1st Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 2nd Author's Name | Takashi Imagawa |
| 2nd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 3rd Author's Name | Hiroyuki Ochi |
| 3rd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
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| Speaker | Author-1 |
| Date Time | 2019-02-28 13:05:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2018-112, HWS2018-75 |
| Volume (vol) | vol.118 |
| Number (no) | no.457(VLD), no.458(HWS) |
| Page | pp.115-120 |
| #Pages | 6 |
| Date of Issue | 2019-02-20 (VLD, HWS) |
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