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Paper Abstract and Keywords
Presentation 2019-03-01 10:00
Synthesis of Full Hardware Implementation of RTOS-Based Systems
Yuuki Oosako, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2018-122 HWS2018-85
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents a method of automatically synthesizing a hardware
design from a set of source codes for a real-time system utilizing an
RTOS. It generates a full hardware implementation where all the
tasks and handlers in the system as well as all the necessary services
provided by the RTOS kernel are implemented as hardware. Every task
and handler is synthesized into an independent hardware module so that
it may run in parallel with the other tasks/handlers as soon as it is
ready. This leads to task switching with extremely low overhead and
reduced computation time both by parallel and hardware execution.
Moreover, this eliminates the necessity of the task queue management;
task scheduling is realized by a relatively simple manager hardware
which instructs each task/handler to run or stall based on the values
of its status variables. Since most of the API calls from
tasks/handlers are reduced to reads/writes of these status variables,
they can be expanded inline into the tasks/handlers' source codes
which are compiled into hardware designs by a high-level synthesizer.
We have implemented a prototype synthesis system which assume the use
of the TOPPERS/ASP3 real-time kernel. A hardware implementation
synthesized from a sample1.c code, bundled in the TOPPERS/ASP3
release, took 23 cycles for waking up a waiting task and only 1 cycle
for activating an interrupt handler.
Keyword (in Japanese) (See Japanese page) 
(in English) Real-Time Systems / RTOS / System Synthesis / Hardware Accelerator / TOPPERS/ASP3 / High-Level Synthesis / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 457, VLD2018-122, pp. 175-180, Feb. 2019.
Paper # VLD2018-122 
Date of Issue 2019-02-20 (VLD, HWS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2018-122 HWS2018-85

Conference Information
Committee HWS VLD  
Conference Date 2019-02-27 - 2019-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Ken Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon, Hardware Security, etc. 
Paper Information
Registration To VLD 
Conference Code 2019-02-HWS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Synthesis of Full Hardware Implementation of RTOS-Based Systems 
Sub Title (in English)  
Keyword(1) Real-Time Systems  
Keyword(2) RTOS  
Keyword(3) System Synthesis  
Keyword(4) Hardware Accelerator  
Keyword(5) TOPPERS/ASP3  
Keyword(6) High-Level Synthesis  
Keyword(7)  
Keyword(8)  
1st Author's Name Yuuki Oosako  
1st Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
2nd Author's Name Nagisa Ishiura  
2nd Author's Affiliation Kwansei Gakuin University (Kwansei Gakuin Univ.)
3rd Author's Name Hiroyuki Tomiyama  
3rd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
4th Author's Name Hiroyuki Kanbara  
4th Author's Affiliation ASTEM RI (ASTEM)
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Speaker Author-1 
Date Time 2019-03-01 10:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2018-122, HWS2018-85 
Volume (vol) vol.118 
Number (no) no.457(VLD), no.458(HWS) 
Page pp.175-180 
#Pages 6 
Date of Issue 2019-02-20 (VLD, HWS) 

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