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Paper Abstract and Keywords
Presentation 2019-07-23 14:50
An FPGA Implementation of Aggregate Signature Schemes with Pipelined Modular Multiplier
Yota Okuaki, Junichi Sakamoto, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) ISEC2019-30 SITE2019-24 BioX2019-22 HWS2019-25 ICSS2019-28 EMM2019-33
Abstract (in Japanese) (See Japanese page) 
(in English) Expectations for "Advanced Cryptography" are increasing in order to enhance the security of cyber physical systems and cloud computing. "Searchable encryption", which can perform database search while encrypted, and "Aggregate signature", which can perform signature verification on multiple messages collectively, are specific examples of Advanced Cryptography. A major component to realize Advanced Cryptography is pairing calculations. A high-speed hardware-based pairing implementation using a pipelined Montgomery modular multiplier is available. In addition to pairing, it is also essential to speed up the implementation of MapToPoint function, which maps arbitrary data to points on elliptic curves. We can execute verification process for aggregate signature faster than software implementation by calculating MapToPoint function on multiple input signed messages on FPGA using pipelined modular multiplier.
Keyword (in Japanese) (See Japanese page) 
(in English) Hardware Security / Pairing Encryption / FPGA Implementation / Pipeline Implementation / Aggregate Signature / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 143, HWS2019-25, pp. 157-162, July 2019.
Paper # HWS2019-25 
Date of Issue 2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ISEC2019-30 SITE2019-24 BioX2019-22 HWS2019-25 ICSS2019-28 EMM2019-33

Conference Information
Conference Date 2019-07-23 - 2019-07-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Kochi University of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Security, etc. 
Paper Information
Registration To HWS 
Conference Code 2019-07-ISEC-SITE-ICSS-EMM-HWS-BioX-CSEC-SPT 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An FPGA Implementation of Aggregate Signature Schemes with Pipelined Modular Multiplier 
Sub Title (in English)
Keyword(1) Hardware Security  
Keyword(2) Pairing Encryption  
Keyword(3) FPGA Implementation  
Keyword(4) Pipeline Implementation  
Keyword(5) Aggregate Signature  
1st Author's Name Yota Okuaki  
1st Author's Affiliation Yokohama National University (YNU)
2nd Author's Name Junichi Sakamoto  
2nd Author's Affiliation Yokohama National University (YNU)
3rd Author's Name Daisuke Fujimoto  
3rd Author's Affiliation Yokohama National University (YNU)
4th Author's Name Tsutomu Matsumoto  
4th Author's Affiliation Yokohama National University (YNU)
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Speaker Author-1 
Date Time 2019-07-23 14:50:00 
Presentation Time 25 minutes 
Registration for HWS 
Paper # ISEC2019-30, SITE2019-24, BioX2019-22, HWS2019-25, ICSS2019-28, EMM2019-33 
Volume (vol) vol.119 
Number (no) no.140(ISEC), no.141(SITE), no.142(BioX), no.143(HWS), no.144(ICSS), no.145(EMM) 
Page pp.157-162 
Date of Issue 2019-07-16 (ISEC, SITE, BioX, HWS, ICSS, EMM) 

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