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Paper Abstract and Keywords
Presentation 2019-11-13 11:20
A New ATPG-based Logic Optimization Method by Removing the Redundant Multiple Faults
Peikun Wang, Amir Masaud Gharehbaghi, Masahiro Fujita (The Univ. of Tokyo) VLD2019-32 DC2019-56
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a new ATPG-based logic optimization method by removing the redundant multiple faults. In order to find the redundant multiple faults, the incremental ATPG method is applied to quickly filter out the non-redundant faults. The multiple redundancies are eliminated from higher cardinality to lower cardinality; and hence, more redundancies can be removed. The experimental results up to redundant triple faults indicate that the proposed method can remove more redundancy comparing to the redundancy removal command in the synthesis tool SIS.
Keyword (in Japanese) (See Japanese page) 
(in English) logic optimization / redundant multiple faults / incremental fault selection method / / / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 282, VLD2019-32, pp. 19-22, Nov. 2019.
Paper # VLD2019-32 
Date of Issue 2019-11-06 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2019-32 DC2019-56

Conference Information
Committee VLD DC CPSY RECONF ICD IE IPSJ-SLDM IPSJ-EMB 
Conference Date 2019-11-13 - 2019-11-15 
Place (in Japanese) (See Japanese page) 
Place (in English) Ehime Prefecture Gender Equality Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2019 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2019-11-VLD-DC-CPSY-RECONF-ICD-IE-SLDM-EMB-ARC 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A New ATPG-based Logic Optimization Method by Removing the Redundant Multiple Faults 
Sub Title (in English)  
Keyword(1) logic optimization  
Keyword(2) redundant multiple faults  
Keyword(3) incremental fault selection method  
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1st Author's Name Peikun Wang  
1st Author's Affiliation The University of Tokyo (The Univ. of Tokyo)
2nd Author's Name Amir Masaud Gharehbaghi  
2nd Author's Affiliation The University of Tokyo (The Univ. of Tokyo)
3rd Author's Name Masahiro Fujita  
3rd Author's Affiliation The University of Tokyo (The Univ. of Tokyo)
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Speaker Author-1 
Date Time 2019-11-13 11:20:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2019-32, DC2019-56 
Volume (vol) vol.119 
Number (no) no.282(VLD), no.283(DC) 
Page pp.19-22 
#Pages 4 
Date of Issue 2019-11-06 (VLD, DC) 

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