Paper Abstract and Keywords |
Presentation |
2020-01-17 13:15
[Poster Presentation]
Optimization of a Josephson latching driver using 10-kA/cm2 Nb process for a Josephson-CMOS hybrid memory Yuki Hironaka, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama Natl. Univ.) SCE2019-47 Link to ES Tech. Rep. Archives: SCE2019-47 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Josephson digital circuits such as single flux quantum circuits have a great potential for future high-end computing systems in terms of their capability of high-speed operation and low power consumption. One of the most critical challenges that Josephson circuits currently have is a memory; there is no reasonable solution for a large-capacity Josephson memory yet, due to the low integration degree and low driving ability of Josephson devices. A Josephson-CMOS hybrid memory is expected as a good solution for Josephson-compatible large-scale memory systems.
A Josephson latching driver, which converts an SFQ pulse input to a voltage level signal, is a key component of the Josephson-CMOS hybrid memory. In this study, we conducted parameter optimization of the Josephson latching driver using the 10-kA/cm2 Nb advanced process in National Institute of Advanced Industrial Science and Technology (AIST). The basic structure is following the circuit that was designed and demonstrated in the 2.5-kA/cm2 Nb standard process, where the circuit is composed of a Suzuki stack with 17/16-Josephson junctions and a 4JL gate as a pre-amplifier. Circuit parameters were modified considering improved junction characteristics in high-Jc processes. In order to compensate the low driving ability of Josephson junctions due to its smaller subgap resistance, we increased the load resistance as well as the critical current of the 4JL gate, so that the bias margins of both Suzuki Stack and 4JL gate were increased. In the experiment, the correct operation of a fabricated circuit was obtained at a target frequency of 2 GHz. The correct operation of the circuit with CMOS circuits was also demonstrated at low frequencies. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Josephson latching driver / Suzuki stack / voltage driver / Josephson-CMOS hybrid memory / Josephson circuit / / / |
Reference Info. |
IEICE Tech. Rep., vol. 119, no. 369, SCE2019-47, pp. 73-74, Jan. 2020. |
Paper # |
SCE2019-47 |
Date of Issue |
2020-01-09 (SCE) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
SCE2019-47 Link to ES Tech. Rep. Archives: SCE2019-47 |
Conference Information |
Committee |
SCE |
Conference Date |
2020-01-16 - 2020-01-17 |
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(See Japanese page) |
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Paper Information |
Registration To |
SCE |
Conference Code |
2020-01-SCE |
Language |
English |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Optimization of a Josephson latching driver using 10-kA/cm2 Nb process for a Josephson-CMOS hybrid memory |
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Keyword(1) |
Josephson latching driver |
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Suzuki stack |
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voltage driver |
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Josephson-CMOS hybrid memory |
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Josephson circuit |
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1st Author's Name |
Yuki Hironaka |
1st Author's Affiliation |
Yokohama National University (Yokohama Natl. Univ.) |
2nd Author's Name |
Yuki Yamanashi |
2nd Author's Affiliation |
Yokohama National University (Yokohama Natl. Univ.) |
3rd Author's Name |
Nobuyuki Yoshikawa |
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Yokohama National University (Yokohama Natl. Univ.) |
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Speaker |
Author-1 |
Date Time |
2020-01-17 13:15:00 |
Presentation Time |
135 minutes |
Registration for |
SCE |
Paper # |
SCE2019-47 |
Volume (vol) |
vol.119 |
Number (no) |
no.369 |
Page |
pp.73-74 |
#Pages |
2 |
Date of Issue |
2020-01-09 (SCE) |
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