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Paper Abstract and Keywords
Presentation 2020-02-26 11:35
Method for Inserting Fault-Detection-Strengthened Test Point under Multi-cycle Testing
Tomoki Aono, Norihiro Nakaoka, Shyu Saikou, Wang Senling, Higami Yoshinobu, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Youichi Maeda, Jun Matsushima (Renesas) DC2019-89
Abstract (in Japanese) (See Japanese page) 
(in English) For guaranteeing the functional safety of an in-vehicle system, a power-on self-test (POST) is required to test the devices of system with high fault coverage (e.g.: >90% for stuck-at faults) and within extremely limited test application time TAT (e.g.: <50ms) at the system startup. Multi-cycle test looks promising a way to satisfy these requirements of POST, however, faces a challenge of fault detection degradation (FDD) problem that would obstruct the further test reduction of multi-cycle test. This paper propose a test point insertion approach to address such problem for improving the testability of CUT (circuit under test) in multi-cycle test scheme. In the proposed approach, we also proposed the selection algorithm to determine the most effective location for test point insertion in consideration of the testability of the time-expanded logic circuit under multi-cycle test. We show the effectiveness of the proposed method by an evaluation experiments on benchmark circuits.
Keyword (in Japanese) (See Japanese page) 
(in English) POST / LBIST / Multi-cycle Test / Functional Safety / ISO26262 / / /  
Reference Info. IEICE Tech. Rep., vol. 119, no. 420, DC2019-89, pp. 19-24, Feb. 2020.
Paper # DC2019-89 
Date of Issue 2020-02-19 (DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2020-02-26 - 2020-02-26 
Place (in Japanese) (See Japanese page) 
Place (in English)  
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Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2020-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Method for Inserting Fault-Detection-Strengthened Test Point under Multi-cycle Testing 
Sub Title (in English)  
Keyword(1) POST  
Keyword(2) LBIST  
Keyword(3) Multi-cycle Test  
Keyword(4) Functional Safety  
Keyword(5) ISO26262  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Tomoki Aono  
1st Author's Affiliation Ehime Univercity (Ehime Univ.)
2nd Author's Name Norihiro Nakaoka  
2nd Author's Affiliation Ehime Univercity (Ehime Univ.)
3rd Author's Name Shyu Saikou  
3rd Author's Affiliation Ehime Univercity (Ehime Univ.)
4th Author's Name Wang Senling  
4th Author's Affiliation Ehime Univercity (Ehime Univ.)
5th Author's Name Higami Yoshinobu  
5th Author's Affiliation Ehime Univercity (Ehime Univ.)
6th Author's Name Hiroshi Takahashi  
6th Author's Affiliation Ehime Univercity (Ehime Univ.)
7th Author's Name Hiroyuki Iwata  
7th Author's Affiliation Renesas Electronics Corporation (Renesas)
8th Author's Name Youichi Maeda  
8th Author's Affiliation Renesas Electronics Corporation (Renesas)
9th Author's Name Jun Matsushima  
9th Author's Affiliation Renesas Electronics Corporation (Renesas)
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Speaker Author-1 
Date Time 2020-02-26 11:35:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2019-89 
Volume (vol) vol.119 
Number (no) no.420 
Page pp.19-24 
#Pages
Date of Issue 2020-02-19 (DC) 


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