Paper Abstract and Keywords |
Presentation |
2020-02-26 11:35
Method for Inserting Fault-Detection-Strengthened Test Point under Multi-cycle Testing Tomoki Aono, Norihiro Nakaoka, Shyu Saikou, Wang Senling, Higami Yoshinobu, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Youichi Maeda, Jun Matsushima (Renesas) DC2019-89 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
For guaranteeing the functional safety of an in-vehicle system, a power-on self-test (POST) is required to test the devices of system with high fault coverage (e.g.: >90% for stuck-at faults) and within extremely limited test application time TAT (e.g.: <50ms) at the system startup. Multi-cycle test looks promising a way to satisfy these requirements of POST, however, faces a challenge of fault detection degradation (FDD) problem that would obstruct the further test reduction of multi-cycle test. This paper propose a test point insertion approach to address such problem for improving the testability of CUT (circuit under test) in multi-cycle test scheme. In the proposed approach, we also proposed the selection algorithm to determine the most effective location for test point insertion in consideration of the testability of the time-expanded logic circuit under multi-cycle test. We show the effectiveness of the proposed method by an evaluation experiments on benchmark circuits. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
POST / LBIST / Multi-cycle Test / Functional Safety / ISO26262 / / / |
Reference Info. |
IEICE Tech. Rep., vol. 119, no. 420, DC2019-89, pp. 19-24, Feb. 2020. |
Paper # |
DC2019-89 |
Date of Issue |
2020-02-19 (DC) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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DC2019-89 |
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