| 講演抄録/キーワード |
| 講演名 |
2020-05-29 15:05
A tightly-connected RISC-V manycore processor in a SIMD manner ○Tan Yuxi・Riadh Ben Abdelhamid・Yoshiki Yamaguchi(Tsukuba Univ.) RECONF2020-17 |
| 抄録 |
(和) |
(まだ登録されていません) |
| (英) |
The size and complexity of scientific and industrial applications have grown larger with computational technology development. However, some new issues are arising such as Implementation of scientific algorithms or software development on complicated heterogeneous architecture. Besides, some algorithms require the appropriate architecture for a shortening of computation hours. Here, in this article, a tightly-connected RISC-V manycore processor and its improved type is proposed for Single-Instruction Multiple Data implementation. It relieves the difficulty of parallel program implementation, maximize the parallel efficiency of the program and enables to allow us to use more than 100 cores in a single program easily. |
| キーワード |
(和) |
/ / / / / / / |
| (英) |
SIMD / 2D Torus / RISC-V / FPGA / / / / |
| 文献情報 |
信学技報, vol. 120, no. 36, RECONF2020-17, pp. 91-96, 2020年5月. |
| 資料番号 |
RECONF2020-17 |
| 発行日 |
2020-05-21 (RECONF) |
| ISSN |
Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
査読に ついて |
本技術報告は査読を経ていない技術報告であり,推敲を加えられていずれかの場に発表されることがあります. |
| PDFダウンロード |
RECONF2020-17 |