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| Presentation | 2020-05-29 15:05 A tightly-connected RISC-V manycore processor in a SIMD manner Tan Yuxi, Riadh Ben Abdelhamid, Yoshiki Yamaguchi (Tsukuba Univ.)  RECONF2020-17 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The size and complexity of scientific and industrial applications have grown larger with computational technology development. However, some new issues are arising such as Implementation of scientific algorithms or software development on complicated heterogeneous architecture. Besides, some algorithms require the appropriate architecture for a shortening of computation hours. Here, in this article, a tightly-connected RISC-V manycore processor and its improved type is proposed for Single-Instruction Multiple Data implementation. It relieves the difficulty of parallel program implementation, maximize the parallel efficiency of the program and enables to allow us to use more than 100 cores in a single program easily. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | SIMD / 2D Torus / RISC-V / FPGA / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 120, no. 36, RECONF2020-17, pp. 91-96, May 2020. | |
| Paper # | RECONF2020-17 | |
| Date of Issue | 2020-05-21 (RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Notes on Review | This article is a technical report without peer review, and its polished version will be published elsewhere. | |
| Download PDF | RECONF2020-17 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2020-05-28 - 2020-05-29 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable system, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2020-05-RECONF |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A tightly-connected RISC-V manycore processor in a SIMD manner |
| Sub Title (in English) | |
| Keyword(1) | SIMD |
| Keyword(2) | 2D Torus |
| Keyword(3) | RISC-V |
| Keyword(4) | FPGA |
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| 1st Author's Name | Tan Yuxi |
| 1st Author's Affiliation | University of Tsukuba (Tsukuba Univ.) |
| 2nd Author's Name | Riadh Ben Abdelhamid |
| 2nd Author's Affiliation | University of Tsukuba (Tsukuba Univ.) |
| 3rd Author's Name | Yoshiki Yamaguchi |
| 3rd Author's Affiliation | University of Tsukuba (Tsukuba Univ.) |
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| Speaker | Author-1 |
| Date Time | 2020-05-29 15:05:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2020-17 |
| Volume (vol) | vol.120 |
| Number (no) | no.36 |
| Page | pp.91-96 |
| #Pages | 6 |
| Date of Issue | 2020-05-21 (RECONF) |
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