IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2021-01-19 13:55
Study and evaluation of adiabatic quantum-flux-parametron logic gates using delay-line clocking
Taiki Yamae (Yokohama Natl. Univ./JSPS Research Fellow), Naoki Takeuchi, Nobuyuki Yoshikawa (Yokohama Natl. Univ.) SCE2020-19 Link to ES Tech. Rep. Archives: SCE2020-19
Abstract (in Japanese) (See Japanese page) 
(in English) Adiabatic quantum-flux-parametron (AQFP) is a superconductor logic family, which can operate with low switching energy. In a previous study, we proposed a delay-line clocking and demonstrated a simple AQFP buffer chain operating at 4 GHz with a latency of 10 ps between gates. However, it is not clear that more complex AQFP circuits adopting delay-line clocking can operate as is the case for a buffer chain. In the present study, we study and evaluate the AQFP logic gates adopting delay-line clocking. In delay-line clocking, it is not necessary to insert buffers in each phase because the latency is much smaller than that using conventional clocking scheme. Numerical simulation shows that buffer chain including phase skip buffer can operate with wide operating margins. We also confirm that the AQFP AND and XOR can operate with wide operating margins and latency of several ps in numerical simulations. We fabricate a test circuit including buffer chains, an AND, and an XOR using the AIST 10 kA/cm2 Nb high-speed standard process. The correct operations of a 2-phase skip buffer chain, an AND, and an XOR are confirmed at 5.5, 4, and 3 GHz, respectively, with latency of 20 ps between gates.
Keyword (in Japanese) (See Japanese page) 
(in English) superconducting integrated circuit / adiabatic quantum-flux-parametron (AQFP) / adiabatic logic circuit / / / / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 313, SCE2020-19, pp. 13-18, Jan. 2021.
Paper # SCE2020-19 
Date of Issue 2021-01-12 (SCE) 
ISSN Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SCE2020-19 Link to ES Tech. Rep. Archives: SCE2020-19

Conference Information
Committee SCE  
Conference Date 2021-01-19 - 2021-01-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SCE 
Conference Code 2021-01-SCE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Study and evaluation of adiabatic quantum-flux-parametron logic gates using delay-line clocking 
Sub Title (in English)  
Keyword(1) superconducting integrated circuit  
Keyword(2) adiabatic quantum-flux-parametron (AQFP)  
Keyword(3) adiabatic logic circuit  
1st Author's Name Taiki Yamae  
1st Author's Affiliation Yokohama National University/Research Fellow of Japan Society for the Promotion of Science (Yokohama Natl. Univ./JSPS Research Fellow)
2nd Author's Name Naoki Takeuchi  
2nd Author's Affiliation Yokohama National University (Yokohama Natl. Univ.)
3rd Author's Name Nobuyuki Yoshikawa  
3rd Author's Affiliation Yokohama National University (Yokohama Natl. Univ.)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2021-01-19 13:55:00 
Presentation Time 25 minutes 
Registration for SCE 
Paper # SCE2020-19 
Volume (vol) vol.120 
Number (no) no.313 
Page pp.13-18 
Date of Issue 2021-01-12 (SCE) 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan