Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2021-01-25 17:35
High speed architectures of decimal counters
Shuhei Yanagawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2020-54 CPSY2020-37 RECONF2020-73
Abstract (in Japanese) (See Japanese page) 
(in English) In this study, we propose new architectures for high speed decimal counters. The two kinds of counters are designed using BCD code and abacus number representations respectively, and the design results show that the abacus architecture can be mainly implemented by shifting operations. Previous studies have proposed the use of the abacus number representation in digital systems, proving that adders using the abacus number representation are extremely fast. We also present a new carry look ahead algorithm by which, the carries are stored in some inserting flip-flops and the high speed counters can be implemented.
Keyword (in Japanese) (See Japanese page) 
(in English) dicimal counter / abacus number / Binary coded decimal / / / / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 337, VLD2020-54, pp. 85-89, Jan. 2021.
Paper # VLD2020-54 
Date of Issue 2021-01-18 (VLD, CPSY, RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2020-54 CPSY2020-37 RECONF2020-73

Conference Information
Committee CPSY RECONF VLD IPSJ-ARC IPSJ-SLDM  
Conference Date 2021-01-25 - 2021-01-26 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To VLD 
Conference Code 2021-01-CPSY-RECONF-VLD-ARC-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) High speed architectures of decimal counters 
Sub Title (in English)  
Keyword(1) dicimal counter  
Keyword(2) abacus number  
Keyword(3) Binary coded decimal  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Shuhei Yanagawa  
1st Author's Affiliation Gunma University (Gunma Univ.)
2nd Author's Name Yuuki Tanaka  
2nd Author's Affiliation Gunma University (Gunma Univ.)
3rd Author's Name Shugang Wei  
3rd Author's Affiliation Gunma University (Gunma Univ.)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2021-01-25 17:35:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2020-54, CPSY2020-37, RECONF2020-73 
Volume (vol) vol.120 
Number (no) no.337(VLD), no.338(CPSY), no.339(RECONF) 
Page pp.85-89 
#Pages 5 
Date of Issue 2021-01-18 (VLD, CPSY, RECONF) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan