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| Presentation | 2021-01-28 14:05 [Invited Talk] Secure 3D CMOS Chip Stacks with Backside Buried Metal Power Delivery Networks for Distributed Decoupling Capacitance Kazuki Monta (Kobe Univ.)  SDM2020-51 Link to ES Tech. Rep. Archives: SDM2020-51 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In semiconductor integrated circuits, power signal integrity(PSI) and electromagnetic compatibility caused by power supply noise are critical issues. Secure three-dimensional (3D) CMOS chip stacks with backside buried metal (BBM) routing provide low series impedance and high decoupling capability in a power delivery network (PDN), thanks to its distributed capacitances over a full-chip backside area. The Si demonstrator with cryptographic functionality was fabricated with post-Si wafer-level BBM Cu processing. The capacitance of BBM structure and it’s suppression effect are evaluated. And we also confirm that 3D BBM PDN also effectively reduces power side channel information leakage. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Si substrate backside / Power supply noise / Power signal integrity / On chip monitoring / Electromagnetic compatibility / Side channel leakage / Cryptographic engine / | |
| Reference Info. | IEICE Tech. Rep., vol. 120, no. 352, SDM2020-51, pp. 8-12, Jan. 2021. | |
| Paper # | SDM2020-51 | |
| Date of Issue | 2021-01-21 (SDM) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2020-51 Link to ES Tech. Rep. Archives: SDM2020-51 |
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| Conference Information | |
| Committee | SDM |
| Conference Date | 2021-01-28 - 2021-01-28 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | SDM |
| Conference Code | 2021-01-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Secure 3D CMOS Chip Stacks with Backside Buried Metal Power Delivery Networks for Distributed Decoupling Capacitance |
| Sub Title (in English) | |
| Keyword(1) | Si substrate backside |
| Keyword(2) | Power supply noise |
| Keyword(3) | Power signal integrity |
| Keyword(4) | On chip monitoring |
| Keyword(5) | Electromagnetic compatibility |
| Keyword(6) | Side channel leakage |
| Keyword(7) | Cryptographic engine |
| Keyword(8) | |
| 1st Author's Name | Kazuki Monta |
| 1st Author's Affiliation | Kobe University (Kobe Univ.) |
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| Speaker | Author-1 |
| Date Time | 2021-01-28 14:05:00 |
| Presentation Time | 30 minutes |
| Registration for | SDM |
| Paper # | SDM2020-51 |
| Volume (vol) | vol.120 |
| Number (no) | no.352 |
| Page | pp.8-12 |
| #Pages | 5 |
| Date of Issue | 2021-01-21 (SDM) |
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