Paper Abstract and Keywords |
Presentation |
2021-01-28 17:35
Study of a Hardware Implementation of a Long Short-Term Memory with HDLRuby Yuki Maehara, Ryota Sakai, Lovic Gauthier (NITAC) CAS2020-54 ICTSSL2020-39 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In the recent years, many global companies have attempted to use FPGA for implementing applications in the field of AI such as automatic driving systems and automatic spoken language recognition. In this paper we propose to use HDLRuby, a new hardware description language with high flexibility for designing AI-related FPGA applications. HDLRuby integrates paradigms original for hardware design including object-oriented programming, generic programming, meta programming and reflection, and is designed as a part of the Ruby framework. In this study, we take advantage of these features to implement a long short-term memory neural network, whose architecture is tailored through a limited number of parameters. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / Ruby / HDLRuby / Neural Networks / LSTM / / / |
Reference Info. |
IEICE Tech. Rep., vol. 120, no. 346, CAS2020-54, pp. 85-90, Jan. 2021. |
Paper # |
CAS2020-54 |
Date of Issue |
2021-01-21 (CAS, ICTSSL) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CAS2020-54 ICTSSL2020-39 |
Conference Information |
Committee |
CAS ICTSSL |
Conference Date |
2021-01-28 - 2021-01-29 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Online |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Students session, General session |
Paper Information |
Registration To |
CAS |
Conference Code |
2021-01-CAS-ICTSSL |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Study of a Hardware Implementation of a Long Short-Term Memory with HDLRuby |
Sub Title (in English) |
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FPGA |
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Ruby |
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HDLRuby |
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Neural Networks |
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LSTM |
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1st Author's Name |
Yuki Maehara |
1st Author's Affiliation |
National Institute of Technology, Ariake College (NITAC) |
2nd Author's Name |
Ryota Sakai |
2nd Author's Affiliation |
National Institute of Technology, Ariake College (NITAC) |
3rd Author's Name |
Lovic Gauthier |
3rd Author's Affiliation |
National Institute of Technology, Ariake College (NITAC) |
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Speaker |
Author-1 |
Date Time |
2021-01-28 17:35:00 |
Presentation Time |
20 minutes |
Registration for |
CAS |
Paper # |
CAS2020-54, ICTSSL2020-39 |
Volume (vol) |
vol.120 |
Number (no) |
no.346(CAS), no.347(ICTSSL) |
Page |
pp.85-90 |
#Pages |
6 |
Date of Issue |
2021-01-21 (CAS, ICTSSL) |
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