| IEICE Technical Committee Submission System Conference Paper's Information |
Online Proceedings [Sign in] Tech. Rep. Archives |
| Go Top Page | Go Previous | [Japanese] / [English] |
| Paper Abstract and Keywords | ||
| Presentation | 2021-01-28 17:15 A Hardware Implementation of Neural Networks using HDLRuby, a Ruby-based Hardware Description Language Ryota Sakai, Yuki Maehara, Lovic Gauthier (NITAC)  CAS2020-53 ICTSSL2020-38 |
|
| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In the recent years, FPGAs have been attracting attention as neural network accelerators for their superior performance in terms of latency and power consumption compared to CPU-and GPU-based implementations. In this study we used HDLRuby, a hardware description language including SW paradigms not available in equivalent languages. They make this language very flexible, and we took advantage of these features to freely set the number of layers and for each layer, their activation function, their number of neurons. We implemented the moduleusing the above method, simulatedit using the HDLRuby code and the Verilog HDL code. The Verilog HDLcode provesto be several times longer than the original code. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA / HDLRuby / Ruby / Neural Networks / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 120, no. 346, CAS2020-53, pp. 79-84, Jan. 2021. | |
| Paper # | CAS2020-53 | |
| Date of Issue | 2021-01-21 (CAS, ICTSSL) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CAS2020-53 ICTSSL2020-38 |
|
| Conference Information | |
| Committee | CAS ICTSSL |
| Conference Date | 2021-01-28 - 2021-01-29 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Students session, General session |
| Paper Information | |
| Registration To | CAS |
| Conference Code | 2021-01-CAS-ICTSSL |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Hardware Implementation of Neural Networks using HDLRuby, a Ruby-based Hardware Description Language |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | HDLRuby |
| Keyword(3) | Ruby |
| Keyword(4) | Neural Networks |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Ryota Sakai |
| 1st Author's Affiliation | National Institute of Technology, Ariake College (NITAC) |
| 2nd Author's Name | Yuki Maehara |
| 2nd Author's Affiliation | National Institute of Technology, Ariake College (NITAC) |
| 3rd Author's Name | Lovic Gauthier |
| 3rd Author's Affiliation | National Institute of Technology, Ariake College (NITAC) |
| 4th Author's Name | |
| 4th Author's Affiliation | () |
| 5th Author's Name | |
| 5th Author's Affiliation | () |
| 6th Author's Name | |
| 6th Author's Affiliation | () |
| 7th Author's Name | |
| 7th Author's Affiliation | () |
| 8th Author's Name | |
| 8th Author's Affiliation | () |
| 9th Author's Name | |
| 9th Author's Affiliation | () |
| 10th Author's Name | |
| 10th Author's Affiliation | () |
| 11th Author's Name | |
| 11th Author's Affiliation | () |
| 12th Author's Name | |
| 12th Author's Affiliation | () |
| 13th Author's Name | |
| 13th Author's Affiliation | () |
| 14th Author's Name | |
| 14th Author's Affiliation | () |
| 15th Author's Name | |
| 15th Author's Affiliation | () |
| 16th Author's Name | |
| 16th Author's Affiliation | () |
| 17th Author's Name | |
| 17th Author's Affiliation | () |
| 18th Author's Name | |
| 18th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2021-01-28 17:15:00 |
| Presentation Time | 20 minutes |
| Registration for | CAS |
| Paper # | CAS2020-53, ICTSSL2020-38 |
| Volume (vol) | vol.120 |
| Number (no) | no.346(CAS), no.347(ICTSSL) |
| Page | pp.79-84 |
| #Pages | 6 |
| Date of Issue | 2021-01-21 (CAS, ICTSSL) |
[Return to Top Page]