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Paper Abstract and Keywords
Presentation 2021-02-05 14:00
Multiple Target Test Generation Method using Test Scheduling Information of RTL Hardware Elements
Ryuki Asami, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2020-74
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, since the test cost for large-scale integrated circuits has increased, design-for-testability methods for concurrent testing to reduce the number of test patterns have been proposed. In the conventional methods, concurrent testing for the hardware element at register transfer level (RTL) is realized by designing the control signal that enables concurrent testing for RTL hardware elements on state transitions of invalid states in controllers. However, general automatic test pattern generation tools do not always consider concurrent testing, and the effect for reduction of the number of test patterns is not high compared to the estimated value at RTL. In this paper, to further reduce the number of test patterns, we propose a multiple target test generation method using test scheduling information of RTL hardware elements that considers concurrent testing. Experimental results show that the proposed method could reduce the number of test patterns by 2 to 20% compared to test generation without RTL test scheduling information.
Keyword (in Japanese) (See Japanese page) 
(in English) Multiple target test generation / parallel test / test compaction / Partial MaxSAT / / / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 358, DC2020-74, pp. 30-35, Feb. 2021.
Paper # DC2020-74 
Date of Issue 2021-01-29 (DC) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2021-02-05 - 2021-02-05 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2021-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Multiple Target Test Generation Method using Test Scheduling Information of RTL Hardware Elements 
Sub Title (in English)  
Keyword(1) Multiple target test generation  
Keyword(2) parallel test  
Keyword(3) test compaction  
Keyword(4) Partial MaxSAT  
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1st Author's Name Ryuki Asami  
1st Author's Affiliation Nihon University (Nihon Univ)
2nd Author's Name Toshinori Hosokawa  
2nd Author's Affiliation Nihon University (Nihon Univ)
3rd Author's Name Hiroshi Yamazaki  
3rd Author's Affiliation Nihon University (Nihon Univ)
4th Author's Name Masayoshi Yoshimura  
4th Author's Affiliation Kyoto Sangyo University (Kyoto Sangyo Univ)
5th Author's Name Masayuki Arai  
5th Author's Affiliation Nihon University (Nihon Univ)
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Speaker Author-1 
Date Time 2021-02-05 14:00:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2020-74 
Volume (vol) vol.120 
Number (no) no.358 
Page pp.30-35 
#Pages 6 
Date of Issue 2021-01-29 (DC) 

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