講演抄録/キーワード |
講演名 |
2021-03-03 13:25
[記念講演]Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization ○TaiYu Cheng(Osaka Univ.)・Yutaka Masuda(Nagoya Univ.)・Jun Nagayama・Yoichi Momiyama(Socionext Inc.)・Jun Chen・Masanori Hashimoto(Osaka Univ.) VLD2020-72 HWS2020-47 |
抄録 |
(和) |
(まだ登録されていません) |
(英) |
This paper proposes a design optimization methodology that can achieve a mode-wise voltage scalable (MWVS) design with applying the activation-aware slack assignment (ASA). Originally, ASA allocates the timing margin of critical paths with a stochastic treatment of timing errors, which limits its application. Instead, this work employs ASA with guaranteeing no timing errors. The MWVS design is formulated as an optimization problem that minimizes the overall power consumption considering each mode duration, achievable voltage reduction, and accompanied circuit overhead explicitly, and explores the solution space with the downhill simplex algorithm that does not require numerical derivation. For obtaining a solution, i.e., a design, in the optimization process, we exploit the multi-corner multi-mode design flow in a commercial tool for performing mode-wise ASA with sets of false paths dedicated to individual modes. Experimental results based on RISC-V design show that the proposed methodology saves 20% more power compared to the conventional voltage scaling approach and attains 15% gain from the single-mode ASA. Also, the cycle-by-cycle fine-grained false path identification reduced leakage power by 42%. |
キーワード |
(和) |
/ / / / / / / |
(英) |
mode-wise voltage-scaling / activation -aware slack assignment / multi-corner multi-mode / downhill simplex method / / / / |
文献情報 |
信学技報, vol. 120, no. 400, VLD2020-72, pp. 30-30, 2021年3月. |
資料番号 |
VLD2020-72 |
発行日 |
2021-02-24 (VLD, HWS) |
ISSN |
Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
VLD2020-72 HWS2020-47 |
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