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| Presentation | 2021-03-03 13:25 [Memorial Lecture] Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization TaiYu Cheng (Osaka Univ.), Yutaka Masuda (Nagoya Univ.), Jun Nagayama, Yoichi Momiyama (Socionext Inc.), Jun Chen, Masanori Hashimoto (Osaka Univ.)  VLD2020-72 HWS2020-47 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper proposes a design optimization methodology that can achieve a mode-wise voltage scalable (MWVS) design with applying the activation-aware slack assignment (ASA). Originally, ASA allocates the timing margin of critical paths with a stochastic treatment of timing errors, which limits its application. Instead, this work employs ASA with guaranteeing no timing errors. The MWVS design is formulated as an optimization problem that minimizes the overall power consumption considering each mode duration, achievable voltage reduction, and accompanied circuit overhead explicitly, and explores the solution space with the downhill simplex algorithm that does not require numerical derivation. For obtaining a solution, i.e., a design, in the optimization process, we exploit the multi-corner multi-mode design flow in a commercial tool for performing mode-wise ASA with sets of false paths dedicated to individual modes. Experimental results based on RISC-V design show that the proposed methodology saves 20% more power compared to the conventional voltage scaling approach and attains 15% gain from the single-mode ASA. Also, the cycle-by-cycle fine-grained false path identification reduced leakage power by 42%. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | mode-wise voltage-scaling / activation -aware slack assignment / multi-corner multi-mode / downhill simplex method / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 120, no. 400, VLD2020-72, pp. 30-30, March 2021. | |
| Paper # | VLD2020-72 | |
| Date of Issue | 2021-02-24 (VLD, HWS) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2020-72 HWS2020-47 |
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| Conference Information | |
| Committee | HWS VLD |
| Conference Date | 2021-03-03 - 2021-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2021-03-HWS-VLD |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization |
| Sub Title (in English) | |
| Keyword(1) | mode-wise voltage-scaling |
| Keyword(2) | activation -aware slack assignment |
| Keyword(3) | multi-corner multi-mode |
| Keyword(4) | downhill simplex method |
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| 1st Author's Name | TaiYu Cheng |
| 1st Author's Affiliation | Osaka University (Osaka Univ.) |
| 2nd Author's Name | Yutaka Masuda |
| 2nd Author's Affiliation | Nagoya University (Nagoya Univ.) |
| 3rd Author's Name | Jun Nagayama |
| 3rd Author's Affiliation | Socionext Inc. (Socionext Inc.) |
| 4th Author's Name | Yoichi Momiyama |
| 4th Author's Affiliation | Socionext Inc. (Socionext Inc.) |
| 5th Author's Name | Jun Chen |
| 5th Author's Affiliation | Osaka University (Osaka Univ.) |
| 6th Author's Name | Masanori Hashimoto |
| 6th Author's Affiliation | Osaka University (Osaka Univ.) |
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| Speaker | Author-1 |
| Date Time | 2021-03-03 13:25:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2020-72, HWS2020-47 |
| Volume (vol) | vol.120 |
| Number (no) | no.400(VLD), no.401(HWS) |
| Page | p.30 |
| #Pages | 1 |
| Date of Issue | 2021-02-24 (VLD, HWS) |
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