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| 講演名 | 2021-03-03 13:00 ［記念講演］Scheduling Sparse Matrix-Vector Multiplication onto Parallel Communication Architecture ○Mingfei Yu・Ruitao Gao・Masahiro Fujita（Univ. Tokyo）  VLD2020-71 HWS2020-46 |
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| 抄録 | （和） | There is an obvious trend to make use of hardware including many-core CPU, GPU and FPGA, to conduct computationally intensive tasks of deep learning implementations, while a large proportion of which can be formulated into the format of sparse matrix-vector multiplication(SpMV). In contrast with dense matrix-vector multiplication(DMV), scheduling solutions for SpMV targeting parallel processing turn out to be irregular, leading to the dilemma that scheduling problems are time-consuming or even infeasible, especially when the size of the involved matrix increases. In this paper, the minimum scheduling problem of 4*4 SpMV on ring-connected architecture is first studied, with two concepts named multi-Input Vector and multi- Output Vector introduced. Then, we have conducted classification of 4*4 sparse matrices, since parallel schedule for matrices that are able to transform into each other can be simply obtained through mutual transformation, rather than time-consuming search. On account of this theory, we have put forward a decomposition-based algorithm for larger matrices. With the proposed algorithm, search space of the minimum schedule is considerably reduced, as the solvement is guided by known sub-scheduling solutions. Through comparison with an exhaustive search method and a brute force-based parallel scheduling method, the proposed algorithm is proved to be able to offer scheduling solutions of high-equality: averagely utilize 65.27% of the sparseness of the involved matrices and achieve 91.39% of the performance of the solutions generated by exhaustive search, with a remarkable saving of compilation time cost (250 times less) and the best scalability among the above mentioned approaches. |
| （英） | There is an obvious trend to make use of hardware including many-core CPU, GPU and FPGA, to conduct computationally intensive tasks of deep learning implementations, while a large proportion of which can be formulated into the format of sparse matrix-vector multiplication(SpMV). In contrast with dense matrix-vector multiplication(DMV), scheduling solutions for SpMV targeting parallel processing turn out to be irregular, leading to the dilemma that scheduling problems are time-consuming or even infeasible, especially when the size of the involved matrix increases. In this paper, the minimum scheduling problem of 4*4 SpMV on ring-connected architecture is first studied, with two concepts named multi-Input Vector and multi- Output Vector introduced. Then, we have conducted classification of 4*4 sparse matrices, since parallel schedule for matrices that are able to transform into each other can be simply obtained through mutual transformation, rather than time-consuming search. On account of this theory, we have put forward a decomposition-based algorithm for larger matrices. With the proposed algorithm, search space of the minimum schedule is considerably reduced, as the solvement is guided by known sub-scheduling solutions. Through comparison with an exhaustive search method and a brute force-based parallel scheduling method, the proposed algorithm is proved to be able to offer scheduling solutions of high-equality: averagely utilize 65.27% of the sparseness of the involved matrices and achieve 91.39% of the performance of the solutions generated by exhaustive search, with a remarkable saving of compilation time cost (250 times less) and the best scalability among the above mentioned approaches. |
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| キーワード | （和） | sparse matrix-vector multiplication / parallel computing / communication structure / convolutional neural network / / / / |
| （英） | sparse matrix-vector multiplication / parallel computing / communication structure / convolutional neural network / / / / | |
| 文献情報 | 信学技報, vol. 120, no. 400, VLD2020-71, pp. 24-29, 2021年3月. | |
| 資料番号 | VLD2020-71 | |
| 発行日 | 2021-02-24 (VLD, HWS) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| 著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します．(許諾番号：10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| PDFダウンロード | VLD2020-71 HWS2020-46 |
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| 研究会情報 | |
| 研究会 | HWS VLD |
| 開催期間 | 2021-03-03 - 2021-03-04 |
| 開催地（和） | オンライン開催 |
| 開催地（英） | Online |
| テーマ（和） | システムオンシリコンを支える設計技術, ハードウェアセキュリティ, 一般 |
| テーマ（英） | Design Technology for System-on-Silicon, Hardware Security, etc. |
| 講演論文情報の詳細 | |
| 申込み研究会 | VLD |
| 会議コード | 2021-03-HWS-VLD |
| 本文の言語 | 英語 |
| タイトル（和） | |
| サブタイトル（和） | |
| タイトル（英） | Scheduling Sparse Matrix-Vector Multiplication onto Parallel Communication Architecture |
| サブタイトル（英） | |
| キーワード(1)（和/英） | sparse matrix-vector multiplication / sparse matrix-vector multiplication |
| キーワード(2)（和/英） | parallel computing / parallel computing |
| キーワード(3)（和/英） | communication structure / communication structure |
| キーワード(4)（和/英） | convolutional neural network / convolutional neural network |
| キーワード(5)（和/英） | / |
| キーワード(6)（和/英） | / |
| キーワード(7)（和/英） | / |
| キーワード(8)（和/英） | / |
| 第1著者 氏名（和/英/ヨミ） | Mingfei Yu / Mingfei Yu / |
| 第1著者 所属（和/英） | The University of Tokyo (略称： 東大) The University of Tokyo (略称： Univ. Tokyo) |
| 第2著者 氏名（和/英/ヨミ） | Ruitao Gao / Ruitao Gao / |
| 第2著者 所属（和/英） | The University of Tokyo (略称： 東大) The University of Tokyo (略称： Univ. Tokyo) |
| 第3著者 氏名（和/英/ヨミ） | Masahiro Fujita / Masahiro Fujita / |
| 第3著者 所属（和/英） | The University of Tokyo (略称： 東大) The University of Tokyo (略称： Univ. Tokyo) |
| 講演者 | 第1著者 |
| 発表日時 | 2021-03-03 13:00:00 |
| 発表時間 | 25分 |
| 申込先研究会 | VLD |
| 資料番号 | VLD2020-71, HWS2020-46 |
| 巻番号（vol） | vol.120 |
| 号番号（no） | no.400(VLD), no.401(HWS) |
| ページ範囲 | pp.24-29 |
| ページ数 | 6 |
| 発行日 | 2021-02-24 (VLD, HWS) |
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