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Paper Abstract and Keywords
Presentation 2021-03-03 13:00
[Memorial Lecture] Scheduling Sparse Matrix-Vector Multiplication onto Parallel Communication Architecture
Mingfei Yu, Ruitao Gao, Masahiro Fujita (Univ. Tokyo) VLD2020-71 HWS2020-46
Abstract (in Japanese) (See Japanese page) 
(in English) There is an obvious trend to make use of hardware including many-core CPU, GPU and FPGA, to conduct computationally intensive tasks of deep learning implementations, while
a large proportion of which can be formulated into the format of sparse matrix-vector multiplication(SpMV). In contrast with dense matrix-vector multiplication(DMV), scheduling solutions for SpMV targeting parallel processing turn out to be irregular, leading to the dilemma that scheduling problems are time-consuming or even infeasible, especially when the size of the involved matrix increases. In this paper, the minimum scheduling
problem of 4*4 SpMV on ring-connected architecture is first studied, with two concepts named multi-Input Vector and multi- Output Vector introduced. Then, we have conducted classification of 4*4 sparse matrices, since parallel schedule for matrices that are able to transform into each other can be simply obtained through mutual transformation, rather than time-consuming search. On account of this theory, we have put forward a decomposition-based algorithm for larger matrices. With the proposed algorithm, search space of the minimum schedule is considerably reduced, as the solvement is guided by known sub-scheduling solutions. Through comparison with an exhaustive
search method and a brute force-based parallel scheduling method, the proposed algorithm is proved to be able to offer scheduling solutions of high-equality: averagely utilize 65.27%
of the sparseness of the involved matrices and achieve 91.39% of the performance of the solutions generated by exhaustive search, with a remarkable saving of compilation time cost (250 times less) and the best scalability among the above mentioned approaches.
Keyword (in Japanese) (See Japanese page) 
(in English) sparse matrix-vector multiplication / parallel computing / communication structure / convolutional neural network / / / /  
Reference Info. IEICE Tech. Rep., vol. 120, no. 400, VLD2020-71, pp. 24-29, March 2021.
Paper # VLD2020-71 
Date of Issue 2021-02-24 (VLD, HWS) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2020-71 HWS2020-46

Conference Information
Committee HWS VLD  
Conference Date 2021-03-03 - 2021-03-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon, Hardware Security, etc. 
Paper Information
Registration To VLD 
Conference Code 2021-03-HWS-VLD 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Scheduling Sparse Matrix-Vector Multiplication onto Parallel Communication Architecture 
Sub Title (in English)  
Keyword(1) sparse matrix-vector multiplication  
Keyword(2) parallel computing  
Keyword(3) communication structure  
Keyword(4) convolutional neural network  
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Keyword(6)  
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1st Author's Name Mingfei Yu  
1st Author's Affiliation The University of Tokyo (Univ. Tokyo)
2nd Author's Name Ruitao Gao  
2nd Author's Affiliation The University of Tokyo (Univ. Tokyo)
3rd Author's Name Masahiro Fujita  
3rd Author's Affiliation The University of Tokyo (Univ. Tokyo)
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Speaker Author-1 
Date Time 2021-03-03 13:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2020-71, HWS2020-46 
Volume (vol) vol.120 
Number (no) no.400(VLD), no.401(HWS) 
Page pp.24-29 
#Pages 6 
Date of Issue 2021-02-24 (VLD, HWS) 

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