講演抄録/キーワード |
講演名 |
2021-06-09 16:35
A 64-bit RISC-V many-core architecture on FPGAs ○Qixiang Gao・Yoshiki Yamaguchi(Univ. of Tsukuba) RECONF2021-16 |
抄録 |
(和) |
A highly informationized style is constantly evolving due to the semiconductor manufacturing technology development, which has been harnessed for numerous applications such as BigData, AI, and IoT. It requires both high-performance and energy-efficient computing. One of the promising technologies is a many-core architecture design on a single chip. This paper focuses on a 64-bit many-core design for some applications with rigid limits on using electricity like drone control. This article is the first step in the proposition. The many-core design is based on a RISC-V architecture and evaluated on the Xilinx VU9P FPGA platform combined with the Spike simulator. |
(英) |
A highly informationized style is constantly evolving due to the semiconductor manufacturing technology development, which has been harnessed for numerous applications such as BigData, AI, and IoT. It requires both high-performance and energy-efficient computing. One of the promising technologies is a many-core architecture design on a single chip. This paper focuses on a 64-bit many-core design for some applications with rigid limits on using electricity like drone control. This article is the first step in the proposition. The many-core design is based on a RISC-V architecture and evaluated on the Xilinx VU9P FPGA platform combined with the Spike simulator. |
キーワード |
(和) |
FPGA / Many-core / RISC-V / / / / / |
(英) |
FPGA / Many-core / RISC-V / / / / / |
文献情報 |
信学技報, vol. 121, no. 59, RECONF2021-16, pp. 87-92, 2021年6月. |
資料番号 |
RECONF2021-16 |
発行日 |
2021-06-01 (RECONF) |
ISSN |
Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
査読に ついて |
本技術報告は査読を経ていない技術報告であり,推敲を加えられていずれかの場に発表されることがあります. |
PDFダウンロード |
RECONF2021-16 |