Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2021-06-09 16:35
A 64-bit RISC-V many-core architecture on FPGAs
Qixiang Gao, Yoshiki Yamaguchi (Univ. of Tsukuba) RECONF2021-16
Abstract (in Japanese) (See Japanese page) 
(in English) A highly informationized style is constantly evolving due to the semiconductor manufacturing technology development, which has been harnessed for numerous applications such as BigData, AI, and IoT. It requires both high-performance and energy-efficient computing. One of the promising technologies is a many-core architecture design on a single chip. This paper focuses on a 64-bit many-core design for some applications with rigid limits on using electricity like drone control. This article is the first step in the proposition. The many-core design is based on a RISC-V architecture and evaluated on the Xilinx VU9P FPGA platform combined with the Spike simulator.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Many-core / RISC-V / / / / /  
Reference Info. IEICE Tech. Rep., vol. 121, no. 59, RECONF2021-16, pp. 87-92, June 2021.
Paper # RECONF2021-16 
Date of Issue 2021-06-01 (RECONF) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Notes on Review This article is a technical report without peer review, and its polished version will be published elsewhere.
Download PDF RECONF2021-16

Conference Information
Committee RECONF  
Conference Date 2021-06-08 - 2021-06-09 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable system, etc. 
Paper Information
Registration To RECONF 
Conference Code 2021-06-RECONF 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 64-bit RISC-V many-core architecture on FPGAs 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Many-core  
Keyword(3) RISC-V  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Qixiang Gao  
1st Author's Affiliation University of Tsukuba (Univ. of Tsukuba)
2nd Author's Name Yoshiki Yamaguchi  
2nd Author's Affiliation University of Tsukuba (Univ. of Tsukuba)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2021-06-09 16:35:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2021-16 
Volume (vol) vol.121 
Number (no) no.59 
Page pp.87-92 
#Pages 6 
Date of Issue 2021-06-01 (RECONF) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan