| Paper Abstract and Keywords |
| Presentation |
2021-10-19 11:15
High-Efficiency simulation method for evaluating power noise and side-channel leakage in crypto modules Kazuki Monta, Takuji Miki, Makoto Nagata (Kobe Univ.) HWS2021-44 ICD2021-18 |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
In semiconductor integrated circuits of cryptographic modules, the side-channel leakage from power supply noise is critical issue for protecting information security. This paper proposes a high-efficiency power leak simulation methodology of cryptographic ICs. In this methodology, power delivery network model between the power pad of the ASIC and the power node near target circuits is created first. And then, the power supply noise of the target crypto core is obtained by SPICE simulation executed with the power model. In this paper, the simulation methodology was applied to an advanced encryption standard (AES) to evaluate power supply noise. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Crypto Modules / Power Noise / Side-channel leakage / AES / Chip Power Model / SPICE-simulation / / |
| Reference Info. |
IEICE Tech. Rep., vol. 121, no. 207, ICD2021-18, pp. 19-22, Oct. 2021. |
| Paper # |
ICD2021-18 |
| Date of Issue |
2021-10-12 (HWS, ICD) |
| ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Download PDF |
HWS2021-44 ICD2021-18 |
| Conference Information |
| Committee |
HWS ICD |
| Conference Date |
2021-10-19 - 2021-10-19 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Online |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Hardware Security, etc. |
| Paper Information |
| Registration To |
ICD |
| Conference Code |
2021-10-HWS-ICD |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
High-Efficiency simulation method for evaluating power noise and side-channel leakage in crypto modules |
| Sub Title (in English) |
|
| Keyword(1) |
Crypto Modules |
| Keyword(2) |
Power Noise |
| Keyword(3) |
Side-channel leakage |
| Keyword(4) |
AES |
| Keyword(5) |
Chip Power Model |
| Keyword(6) |
SPICE-simulation |
| Keyword(7) |
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| Keyword(8) |
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| 1st Author's Name |
Kazuki Monta |
| 1st Author's Affiliation |
Kobe University (Kobe Univ.) |
| 2nd Author's Name |
Takuji Miki |
| 2nd Author's Affiliation |
Kobe University (Kobe Univ.) |
| 3rd Author's Name |
Makoto Nagata |
| 3rd Author's Affiliation |
Kobe University (Kobe Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2021-10-19 11:15:00 |
| Presentation Time |
25 minutes |
| Registration for |
ICD |
| Paper # |
HWS2021-44, ICD2021-18 |
| Volume (vol) |
vol.121 |
| Number (no) |
no.206(HWS), no.207(ICD) |
| Page |
pp.19-22 |
| #Pages |
4 |
| Date of Issue |
2021-10-12 (HWS, ICD) |