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| Presentation | 2021-12-01 09:45 Low quiescent current LDO with FVF based PSRR enhanced circuit for wearable EEG measurement devices Kenji Mii, Daisuke Kanemoto, Osamu Maida, Tetsuya Hirose (Osaka Univ.)  VLD2021-18 ICD2021-28 DC2021-24 RECONF2021-26 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper proposes a low quiescent current low-dropout regulator (LDO) with a flipped voltage follower (FVF)-based power supply rejection ratio (PSRR)-enhanced circuit. The proposed LDO was designed using a 0.18 μm CMOS process. The designed LDO achieved a PSRR that was improved by 19 dB at 4 kHz, compared with the general configuration with almost the same quiescent current. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Power management / Low-dropout regulator / Low quiescent current / Flipped voltage follower / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 121, no. 277, VLD2021-18, pp. 7-12, Dec. 2021. | |
| Paper # | VLD2021-18 | |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2021-18 ICD2021-28 DC2021-24 RECONF2021-26 |
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| Conference Information | |
| Committee | VLD DC RECONF ICD IPSJ-SLDM |
| Conference Date | 2021-12-01 - 2021-12-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2021 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2021-12-VLD-DC-RECONF-ICD-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low quiescent current LDO with FVF based PSRR enhanced circuit for wearable EEG measurement devices |
| Sub Title (in English) | |
| Keyword(1) | Power management |
| Keyword(2) | Low-dropout regulator |
| Keyword(3) | Low quiescent current |
| Keyword(4) | Flipped voltage follower |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kenji Mii |
| 1st Author's Affiliation | Osaka University (Osaka Univ.) |
| 2nd Author's Name | Daisuke Kanemoto |
| 2nd Author's Affiliation | Osaka University (Osaka Univ.) |
| 3rd Author's Name | Osamu Maida |
| 3rd Author's Affiliation | Osaka University (Osaka Univ.) |
| 4th Author's Name | Tetsuya Hirose |
| 4th Author's Affiliation | Osaka University (Osaka Univ.) |
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| Speaker | Author-1 |
| Date Time | 2021-12-01 09:45:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2021-18, ICD2021-28, DC2021-24, RECONF2021-26 |
| Volume (vol) | vol.121 |
| Number (no) | no.277(VLD), no.278(ICD), no.279(DC), no.280(RECONF) |
| Page | pp.7-12 |
| #Pages | 6 |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) |
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