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| Presentation | 2021-12-01 10:10 A Multilayer Perceptron Training Accelerator using Systolic Array Takeshi Senoo, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara (Toyko Tech)  VLD2021-23 ICD2021-33 DC2021-29 RECONF2021-31 Link to ES Tech. Rep. Archives: ICD2021-33 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Neural networks are being used in various applications, and the demand for fast training with large amounts of data is emerging. For example, a network intrusion detection~(NID) system needs to be trained in a short period to detect attacks based on large amount of traffic logs. We propose a training accelerator as a systolic array on a Xilinx U50 Alveo FPGA card to solve this problem. We found that the accuracy is almost the same as conventional training even when the forward and backward paths are run simultaneously by delaying the weight update. Compared to the Intel Core i9 CPU and NVIDIA RTX 3090 GPU, it was three times faster than the CPU and 2.5 times faster than the GPU. The processing speed per power consumption was 11.5 times better than the CPU and 21.4 times better than the GPU. From these results, we can conclude that implementing a training accelerator on FPGAs as a systolic array can achieve high speed and high energy efficiency. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | neural network / multilayer perceptron / training accelerator / machine learning / intrusion detection system / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 121, no. 280, RECONF2021-31, pp. 37-42, Dec. 2021. | |
| Paper # | RECONF2021-31 | |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2021-23 ICD2021-33 DC2021-29 RECONF2021-31 Link to ES Tech. Rep. Archives: ICD2021-33 |
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| Conference Information | |
| Committee | VLD DC RECONF ICD IPSJ-SLDM |
| Conference Date | 2021-12-01 - 2021-12-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Online |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2021 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2021-12-VLD-DC-RECONF-ICD-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Multilayer Perceptron Training Accelerator using Systolic Array |
| Sub Title (in English) | |
| Keyword(1) | neural network |
| Keyword(2) | multilayer perceptron |
| Keyword(3) | training accelerator |
| Keyword(4) | machine learning |
| Keyword(5) | intrusion detection system |
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| Keyword(7) | |
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| 1st Author's Name | Takeshi Senoo |
| 1st Author's Affiliation | Tokyo Institute of Technology (Toyko Tech) |
| 2nd Author's Name | Akira Jinguji |
| 2nd Author's Affiliation | Tokyo Institute of Technology (Toyko Tech) |
| 3rd Author's Name | Ryosuke Kuramochi |
| 3rd Author's Affiliation | Tokyo Institute of Technology (Toyko Tech) |
| 4th Author's Name | Hiroki Nakahara |
| 4th Author's Affiliation | Tokyo Institute of Technology (Toyko Tech) |
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| Speaker | Author-1 |
| Date Time | 2021-12-01 10:10:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | VLD2021-23, ICD2021-33, DC2021-29, RECONF2021-31 |
| Volume (vol) | vol.121 |
| Number (no) | no.277(VLD), no.278(ICD), no.279(DC), no.280(RECONF) |
| Page | pp.37-42 |
| #Pages | 6 |
| Date of Issue | 2021-11-24 (VLD, ICD, DC, RECONF) |
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