Paper Abstract and Keywords |
Presentation |
2021-12-10 14:00
A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2021-57 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to applied to them. However, functional logic locking method using TTLock are resilient to SAT attack, however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at gate level. In this paper, we propose a logic locking method based on SAT attack and FALL attacks resistance at register transfer level. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Logic Locking / Register Transfer Level / TTLock / SAT Attack / FALL Attacks / Design for Security / / |
Reference Info. |
IEICE Tech. Rep., vol. 121, no. 293, DC2021-57, pp. 13-18, Dec. 2021. |
Paper # |
DC2021-57 |
Date of Issue |
2021-12-03 (DC) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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DC2021-57 |
Conference Information |
Committee |
DC |
Conference Date |
2021-12-10 - 2021-12-10 |
Place (in Japanese) |
(See Japanese page) |
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(See Japanese page) |
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Paper Information |
Registration To |
DC |
Conference Code |
2021-12-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level |
Sub Title (in English) |
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Keyword(1) |
Logic Locking |
Keyword(2) |
Register Transfer Level |
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TTLock |
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SAT Attack |
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FALL Attacks |
Keyword(6) |
Design for Security |
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1st Author's Name |
Atsuya Tsujikawa |
1st Author's Affiliation |
Nihon University (Nihon Univ.) |
2nd Author's Name |
Toshinori Hosokawa |
2nd Author's Affiliation |
Nihon University (Nihon Univ.) |
3rd Author's Name |
Masayoshi Yoshimura |
3rd Author's Affiliation |
Kyoto Sangyo University (Kyoto Sangyo Univ.) |
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Speaker |
Author-1 |
Date Time |
2021-12-10 14:00:00 |
Presentation Time |
20 minutes |
Registration for |
DC |
Paper # |
DC2021-57 |
Volume (vol) |
vol.121 |
Number (no) |
no.293 |
Page |
pp.13-18 |
#Pages |
6 |
Date of Issue |
2021-12-03 (DC) |
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