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Paper Abstract and Keywords
Presentation 2022-01-23 10:15
Analog CMOS implementation of majority logic for neuromorphic circuit applications
Satoshi Ono, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto (Tohoku Univ.), Yasushi Yuminaka (Gunma Univ.), Shigeo Sato (Tohoku Univ.) NC2021-41
Abstract (in Japanese) (See Japanese page) 
(in English) A majority logic circuit is a circuit whose output is the majority value of multiple binary inputs. In addition to its conventional applications as a fault tolerant system, the majority circuit is also expected to be used as a low-power neuron circuit in binary neural networks. However, when the majority logic is implemented in digital circuits, its size and power consumption increase rapidly with the number of inputs. In this study, we used the 0.18 µm CMOS technology to design an analog majority logic circuit that enables a significant reduction in the number of transistors. We show that the majority logic properly operates even when the number of inputs is increased up to 101 and is robust against fluctuations in transistor size.
Keyword (in Japanese) (See Japanese page) 
(in English) Majority logic / Analog circuit implementation / Binary neural network (BNN) / / / / /  
Reference Info. IEICE Tech. Rep., vol. 121, no. 338, NC2021-41, pp. 45-48, Jan. 2022.
Paper # NC2021-41 
Date of Issue 2022-01-14 (NC) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF NC2021-41

Conference Information
Committee NLP MICT MBE NC  
Conference Date 2022-01-21 - 2022-01-23 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To NC 
Conference Code 2022-01-NLP-MICT-MBE-NC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Analog CMOS implementation of majority logic for neuromorphic circuit applications 
Sub Title (in English)  
Keyword(1) Majority logic  
Keyword(2) Analog circuit implementation  
Keyword(3) Binary neural network (BNN)  
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1st Author's Name Satoshi Ono  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Satoshi Moriya  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Yuka Kanke  
3rd Author's Affiliation Tohoku University (Tohoku Univ.)
4th Author's Name Hideaki Yamamoto  
4th Author's Affiliation Tohoku University (Tohoku Univ.)
5th Author's Name Yasushi Yuminaka  
5th Author's Affiliation Gunma University (Gunma Univ.)
6th Author's Name Shigeo Sato  
6th Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker Author-1 
Date Time 2022-01-23 10:15:00 
Presentation Time 25 minutes 
Registration for NC 
Paper # NC2021-41 
Volume (vol) vol.121 
Number (no) no.338 
Page pp.45-48 
#Pages 4 
Date of Issue 2022-01-14 (NC) 

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