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Paper Abstract and Keywords
Presentation 2022-03-01 13:45
A Logic Locking Method based on SFLL-hd at Register Transfer Level
Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.) DC2021-72
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, with the increase of VLSI integration, LSI design companies utilize circuit design information, called IP cores from IP vendors in order to reduce design costs.
However, since IP cores are digital data, it is easy to infringe copyright by copying, etc. Therefore, it is important to take measures against copyright infringement of IP cores.
As a design method for copyright protection of IP cores, a method called logical encryption has been proposed.
On the other hand, efficient attack methods against logical encryption, such as SAT and FALL attacks, have been proposed. Therefore, there is a need for logical encryption that is resistant to these attack methods.
In this paper, we propose a method for RTL design based on SFLL-hd, which is resistant to SAT and FALL attacks.
For controllers at RTL, we show an algorithm to find a correct key input to realize SFLL-hd. Experimental results show that the proposed method is resistant to the FALL attack.
Keyword (in Japanese) (See Japanese page) 
(in English) Logic Locking / SAT attack / FALL attack / RTL / / / /  
Reference Info. IEICE Tech. Rep., vol. 121, no. 388, DC2021-72, pp. 45-50, March 2022.
Paper # DC2021-72 
Date of Issue 2022-02-22 (DC) 
ISSN Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2022-03-01 - 2022-03-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2022-03-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Logic Locking Method based on SFLL-hd at Register Transfer Level 
Sub Title (in English)  
Keyword(1) Logic Locking  
Keyword(2) SAT attack  
Keyword(3) FALL attack  
Keyword(4) RTL  
1st Author's Name Yohei Noguchi  
1st Author's Affiliation Kyoto Sangyo University (Kyoto Sangyo Univ.)
2nd Author's Name Masayoshi Yoshimura  
2nd Author's Affiliation Kyoto Sangyo University (Kyoto Sangyo Univ.)
3rd Author's Name Atsuya Tsujikawa  
3rd Author's Affiliation Nihon University (Nihon Univ.)
4th Author's Name Toshinori Hosokawa  
4th Author's Affiliation Nihon University (Nihon Univ.)
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Speaker Author-1 
Date Time 2022-03-01 13:45:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2021-72 
Volume (vol) vol.121 
Number (no) no.388 
Page pp.45-50 
Date of Issue 2022-02-22 (DC) 

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