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Paper Abstract and Keywords
Presentation 2022-08-10 16:00
IC with Integrated Imager and Ultra-Low Latency All-Digital In-Imager 2D Binary Convolutional Neural Network Accelerator for Image Classification
Ruizhi Wang, Cheng-Hsuan Wu, Makoto Takamiya (The Univ. of Tokyo) SDM2022-53 ICD2022-21
Abstract (in Japanese) (See Japanese page) 
(in English) In the field of real-time image recognition, the computing latency of convolutional neural network become an issue. In this paper, we propose an all-digital in-imager 2D binary convolutional neural network (II2D-BNN) architecture for low-latency convolutional neural network computation. In II2D-BNN, multiply-accumulate operations (MACs) are processed inside the imager array parallelly in 2D, which makes convolutional operations be realized with ultra-low latency independent of input image size. A 30 × 30 II2D-BNN accelerator IC integrating imager circuit is fabricated with the 180 nm CMOS process. It achieved a 3.22 μs/kernel latency on the first layer convolution at the power supply of 1 V and the clock frequency of 35.7 MHz, reducing 80.5 % of latency compared with the state-of-the-art in/near-imager-computing work.
Keyword (in Japanese) (See Japanese page) 
(in English) Convolutional neural network / Ultra-low-latency / Batch-processing-in-2D / In-imager-computing / Image classification / / /  
Reference Info. IEICE Tech. Rep., vol. 122, no. 149, ICD2022-21, pp. 87-92, Aug. 2022.
Paper # ICD2022-21 
Date of Issue 2022-08-01 (SDM, ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2022-53 ICD2022-21

Conference Information
Committee ICD SDM ITE-IST  
Conference Date 2022-08-08 - 2022-08-10 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications 
Paper Information
Registration To ICD 
Conference Code 2022-08-ICD-SDM-IST 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) IC with Integrated Imager and Ultra-Low Latency All-Digital In-Imager 2D Binary Convolutional Neural Network Accelerator for Image Classification 
Sub Title (in English)  
Keyword(1) Convolutional neural network  
Keyword(2) Ultra-low-latency  
Keyword(3) Batch-processing-in-2D  
Keyword(4) In-imager-computing  
Keyword(5) Image classification  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Ruizhi Wang  
1st Author's Affiliation University of Tokyo (The Univ. of Tokyo)
2nd Author's Name Cheng-Hsuan Wu  
2nd Author's Affiliation University of Tokyo (The Univ. of Tokyo)
3rd Author's Name Makoto Takamiya  
3rd Author's Affiliation University of Tokyo (The Univ. of Tokyo)
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Speaker Author-1 
Date Time 2022-08-10 16:00:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # SDM2022-53, ICD2022-21 
Volume (vol) vol.122 
Number (no) no.148(SDM), no.149(ICD) 
Page pp.87-92 
#Pages 6 
Date of Issue 2022-08-01 (SDM, ICD) 

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