Paper Abstract and Keywords |
Presentation |
2022-11-30 10:45
Prototype and evaluation of 4-input variable logic circuit with FGC using neuron CMOS inverter Shoma Ito, Daishi Nishiguchi, Masaaki Fukuhara (Tokai Univ.) VLD2022-45 ICD2022-62 DC2022-61 RECONF2022-68 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Logic elements of FPGA generally use Look-Up Table (LUT) circuits, and the most common types of LUT are 4-input and 6-input due to area efficiency. We proposed a 4-input Variable Logic Circuit with FGC using neuron CMOS inverters (4 in VLC) as an alternative circuit to the 4-input LUT, and verified the FGC and variable logic operation of the 4 in VLC using HSPICE simulations. In this paper, we make a prototype chip of the 4 in VLC with Rohm 0.18um process, evaluate the FGC operation and variable logic operation, and compare the simulation results with the actual device behavior. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Neuron CMOS inverter / Variable Logic Circuit / FPGA / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 122, no. 284, ICD2022-62, pp. 150-155, Nov. 2022. |
Paper # |
ICD2022-62 |
Date of Issue |
2022-11-21 (VLD, ICD, DC, RECONF) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2022-45 ICD2022-62 DC2022-61 RECONF2022-68 |
Conference Information |
Committee |
VLD DC RECONF ICD IPSJ-SLDM |
Conference Date |
2022-11-28 - 2022-11-30 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
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Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2022 -New Field of VLSI Design- |
Paper Information |
Registration To |
ICD |
Conference Code |
2022-11-VLD-DC-RECONF-ICD-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Prototype and evaluation of 4-input variable logic circuit with FGC using neuron CMOS inverter |
Sub Title (in English) |
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Neuron CMOS inverter |
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Variable Logic Circuit |
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FPGA |
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1st Author's Name |
Shoma Ito |
1st Author's Affiliation |
Tokai University (Tokai Univ.) |
2nd Author's Name |
Daishi Nishiguchi |
2nd Author's Affiliation |
Tokai University (Tokai Univ.) |
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Masaaki Fukuhara |
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Tokai University (Tokai Univ.) |
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Speaker |
Author-1 |
Date Time |
2022-11-30 10:45:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
VLD2022-45, ICD2022-62, DC2022-61, RECONF2022-68 |
Volume (vol) |
vol.122 |
Number (no) |
no.283(VLD), no.284(ICD), no.285(DC), no.286(RECONF) |
Page |
pp.150-155 |
#Pages |
6 |
Date of Issue |
2022-11-21 (VLD, ICD, DC, RECONF) |
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