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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Minako Ikeda (NTT)
Vice Chair Shigetoshi Nakatake (Univ. of Kitakyushu)
Secretary Makoto Miyamura (NBS), Masashi Imai (Hirosaki Univ.)
Assistant Takuma Nishimoto (Hitachi)

Technical Committee on Integrated Circuits and Devices (ICD) [schedule] [select]
Chair Masafumi Takahashi (Kioxia)
Vice Chair Makoto Ikeda (Univ. of Tokyo)
Secretary Koji Nii (TSMC), Kosuke Miyaji (Shinshu Univ.)
Assistant Yoshiaki Yoshihara (KIOXIA), Jun Shiomi (Osaka Univ.), Takeshi Kuboki (Sony Semiconductor Solutions)

Technical Committee on Dependable Computing (DC) [schedule] [select]
Chair Tatsuhiro Tsuchiya (Osaka Univ.)
Vice Chair Toshinori Hosokawa (Nihon Univ.)
Secretary Masayuki Arai (Nihon Univ.), Kazuteru Namba (Chiba Univ.)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Kentaro Sano (RIKEN)
Vice Chair Yoshiki Yamaguchi (Tsukuba Univ.), Tomonori Izumi (Ritsumeikan Univ.)
Secretary Yuuki Kobayashi (NEC), Yukinori Sato (Toyohashi Univ. of Tech.)
Assistant Yukitaka Takemura (INTEL), Yasunori Osana (Ryukyu Univ.)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Hiroyuki Ochi (Ritsumeikan Univ.)
Secretary Kazushi Kawamura (Tokyo Inst. of Tech.), Takashi Imagawa (Meiji Univ.), Hiroki Hosoda (Sony Semiconductor Solutions), Yuki Tanaka (HITACHI)

Conference Date Mon, Nov 28, 2022 13:00 - 18:00
Tue, Nov 29, 2022 09:15 - 18:30
Wed, Nov 30, 2022 09:30 - 17:30
Topics Design Gaia 2022 -New Field of VLSI Design- 
Conference Place Kanazawa Bunka Hall 
Address 15-1 Takaoka, Kanazawa, Ishikawa, 920-0864 Japan
Transportation Guide https://www.bunka-h.gr.jp/access/
Sponsors This conference is co-sponsored by IEEE CASS Japan Joint Chpater, IEEE CASS Kansai Chapter, IEEE CEDA All Japan Joint Chapter, and IEEE SSCS Kansai Chapter.
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on VLD, DC, RECONF, ICD.

  13:00-13:05 Opening ( 5 min. )
Mon, Nov 28 PM 
13:05 - 14:45
(1)
VLD
13:05-13:30 Development of ASIC Prototype Chip Evaluation System using FPGA-SoM VLD2022-19 ICD2022-36 DC2022-35 RECONF2022-42 Masashi Imai (Hirosaki Univ.), Kenji Kise (Tokyo Tech.), Tomohiro Yoneda (NII)
(2)
VLD
13:30-13:55 A Study on Co-Optimization of logical structure and bit-line placement for Parallel Prefix Adders VLD2022-20 ICD2022-37 DC2022-36 RECONF2022-43 Mineo Kaneko (JAIST)
(3)
VLD
13:55-14:20 A Routing Method by SAT for Set-Pair Routing Problem VLD2022-21 ICD2022-38 DC2022-37 RECONF2022-44 Koki Nagakura, Rintaro Yokoya, Kunihiro Fujiyoshi (Tokyo Univ of A and T)
(4)
VLD
14:20-14:45 A Study of a Design Methodology for Various CGRA based on Diplomacy VLD2022-22 ICD2022-39 DC2022-38 RECONF2022-45 Takuya Kojima (UTokyo/JST PRESTO), Makoto Saito, Hiroshi Nakamura (UTokyo)
Mon, Nov 28 PM 
13:00 - 14:00
(5) 13:00-14:00  
Mon, Nov 28 PM 
14:00 - 16:15
(6) 14:00-16:15  
Mon, Nov 28 PM 
15:00 - 15:50
(7)
DC
15:00-15:25 On reduction of test patterns for a Multiplier Using Approximate Computing VLD2022-23 ICD2022-40 DC2022-39 RECONF2022-46 Shogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ)
(8)
DC
15:25-15:50 A 6T-8T hybrid SRAM for reducing the power of neural network by lowing the operating voltage VLD2022-24 ICD2022-41 DC2022-40 RECONF2022-47 Ruoxi Yu, Kazuteru Namba (Chiba Univ.)
Mon, Nov 28 PM 
16:15 - 18:00
(9) 16:15-18:00  
Tue, Nov 29 AM 
09:15 - 10:30
(10)
DC
09:15-09:40 A Don't Care Filling Method of control signals for controllers to Maximize the Number of Distinguishable Hard ware Element Pairs VLD2022-25 ICD2022-42 DC2022-41 RECONF2022-48 Yui Otsuka, Yuya Chida, Xu Haofeng, Toshinori Hosokawa (Nihon Univ.), Kouji Yamazaki (Meiji Univ.)
(11)
DC
09:40-10:05 Test Generation Merhod based on RTL Design for Diagnosability VLD2022-26 ICD2022-43 DC2022-42 RECONF2022-49 Yuya Chida, Toshinori Hosokawa (Nihon univ.), Koji Yamazaki (Meiji Univ.)
(12)
DC
10:05-10:30 A Seed Generation Method for Multiple Random Pattern Resistant Stuck-at Faults in Built-In Self-Test VLD2022-27 ICD2022-44 DC2022-43 RECONF2022-50 Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.)
Tue, Nov 29 AM 
10:45 - 12:00
(13)
RECONF
10:45-11:10 FPGA-based Accelerators System with Autonomous DMA Engine VLD2022-28 ICD2022-45 DC2022-44 RECONF2022-51 Tomoya Yokono, Yoshiro Yamabe, Kenji Tanaka, Yuki Arikawa, Teruaki Ishizaki (NTT)
(14)
RECONF
11:10-11:35 A Message Passing Interface Library for High-Level Synthesis on M-KUBOS Multi-FPGA systems VLD2022-29 ICD2022-46 DC2022-45 RECONF2022-52 Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano (Keio Univ.)
(15)
RECONF
11:35-12:00 VLD2022-30 ICD2022-47 DC2022-46 RECONF2022-53
  12:00-13:15 Lunch Break ( 75 min. )
Tue, Nov 29 PM 
13:15 - 14:05
(16) 13:15-14:05  
Tue, Nov 29 PM 
14:15 - 15:30
(17)
ICD
14:15-14:40 Method of Halved Interaction Elements with Regularity Arrangement that achieves Independent Double Systems for Scalable Fully Coupled Annealing Processing VLD2022-31 ICD2022-48 DC2022-47 RECONF2022-54 Shinjiro Kitahara, Akari Endo, Taichi Megumi, Takayuki Kawahara (TUS)
(18)
ICD
14:40-15:05 Evaluating system level security of cryptography module VLD2022-32 ICD2022-49 DC2022-48 RECONF2022-55 Takumi Matsumaru, Kazuki Monta (Kobe Univ.), Takaaki Okidono (SCU), Takuji Miki, Makoto Nagata (Kobe Univ.)
(19)
ICD
15:05-15:30 Evaluation of power delivery networks in secure semiconductor systems VLD2022-33 ICD2022-50 DC2022-49 RECONF2022-56 Masaru Mashiba, Kazuki Monta (Kobe Univ.), Takaaki Okidono (SCU), Takuzi Miki, Makoto Nagata (Kobe Univ.)
Tue, Nov 29 PM 
15:45 - 17:25
(20)
VLD
15:45-16:10 NA VLD2022-34 ICD2022-51 DC2022-50 RECONF2022-57 Tomokazu Yoshimura, Shirai Tatsuhiko, Masashi Tawada, Nozomu Togawa (Waseda Univ.)
(21)
VLD
16:10-16:35 N/A VLD2022-35 ICD2022-52 DC2022-51 RECONF2022-58 Soma Kawakami (Waseda Univ.), Dema Ba, Kentaro Ohno, Satoshi Yagi, Junji Teramoto (NTT), Nozomu Togawa (Waseda Univ.)
(22)
VLD
16:35-17:00 N/A VLD2022-36 ICD2022-53 DC2022-52 RECONF2022-59 Keisuke Fukada (Waseda Univ.), Matthieu Parizy (Waseda Univ./Fujitsu LTD.), Yoshinori Tomita (Fujitsu LTD.), Nozomu Togawa (Waseda Univ.)
(23)
VLD
17:00-17:25 N/A VLD2022-37 ICD2022-54 DC2022-53 RECONF2022-60 Yuta Yachi, Masashi Tawada, Nozomu Togawa (Waseda Univ.)
Tue, Nov 29 PM 
17:40 - 18:30
(24) 17:40-18:30  
Wed, Nov 30 AM 
09:30 - 11:10
(25)
VLD
09:30-09:55 Development of 65nm-Cryo-CMOS Circuit Design Library VLD2022-38 ICD2022-55 DC2022-54 RECONF2022-61 Toshitsugu Sakamoto, Makoto Miyamura, Kazunori Funahashi, Koichiro Okamoto, Munehiro Tada (NBS), Takahisa Tanaka, Ken Uchida (Tokyo Univ.), Hiroki Ishikuro (Keio Univ.)
(26)
VLD
09:55-10:20 Proposal of analytical expression for optimal store time of MTJ-based non-volatile flip-flops VLD2022-39 ICD2022-56 DC2022-55 RECONF2022-62 Daiki Yokoyama, Kimiyoshi Usami (SIT), Aika Kamei, Hideharu Amano (Keio Univ.)
(27)
VLD
10:20-10:45 A fast SRAF optimization used LUT based intensity estimation VLD2022-40 ICD2022-57 DC2022-56 RECONF2022-63 Sota Saito, Atsushi Takahashi (Tokyo Tech)
(28)
VLD
10:45-11:10 Mask Optimization Using Voronoi Partition and Iterative Improvement VLD2022-41 ICD2022-58 DC2022-57 RECONF2022-64 Naoki Nonaka, Yukihide Kohira (Univ. of Aizu), Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA)
Wed, Nov 30 AM 
09:30 - 11:10
(29)
ICD
09:30-09:55 A contact angle estimation method using two coplanar capacitive sensors of different sizes VLD2022-42 ICD2022-59 DC2022-58 RECONF2022-65 Tsubasa Furuta, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine (USP)
(30)
ICD
09:55-10:20 Design of Digital Phase-Locked Loop Circuit based on 3rd-Order MASH ΔΣ FDC for Low In-Band Phase Noise VLD2022-43 ICD2022-60 DC2022-59 RECONF2022-66 Ryoga Iwashita, Zule Xu, Masaru Osada, Ryoya Shibata, Yo Kumano, Tetsuya Iizuka (UTokyo)
(31)
ICD
10:20-10:45 Deep Learning-based Hierarchical Object Detection System for High-Resolution Images VLD2022-44 ICD2022-61 DC2022-60 RECONF2022-67 Yusei Horikawa, Makoto Sugaya, Renpei Yoshida, Kazuma Mashiko, Tetsuya Matsumura (Nihon Univ.)
(32)
ICD
10:45-11:10 Prototype and evaluation of 4-input variable logic circuit with FGC using neuron CMOS inverter VLD2022-45 ICD2022-62 DC2022-61 RECONF2022-68 Shoma Ito, Daishi Nishiguchi, Masaaki Fukuhara (Tokai Univ.)
  11:10-12:40 Lunch Break ( 90 min. )
Wed, Nov 30 PM 
12:40 - 13:20
(33) 12:40-13:20  
Wed, Nov 30 PM 
13:20 - 14:10
(34) 13:20-14:10  
Wed, Nov 30 PM 
14:20 - 15:35
(35)
DC
14:20-14:45 On the performance evaluation of a PUF circuit using the Delay Testable Circuit under temperature effects VLD2022-46 ICD2022-63 DC2022-62 RECONF2022-69 Eisuke Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
(36)
DC
14:45-15:10 Evaluation of testing TSVs using the delay testable circuit implemented in a 3D IC VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70 Keigo Takami (Tokushima Univ. Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
(37)
DC
15:10-15:35 FPGA Implementation and Area Evaluation of JTAG Access Mechanism Using Lightweight One-Time Password Authentication Scheme VLD2022-48 ICD2022-65 DC2022-64 RECONF2022-71 Hisashi Okamoto, Jun Ma, Senling Wang, Hiroshi Kai, Hiroshi Takahashi (Ehime Univ), Akihiro Shimizu (Kochi Univ. of Technology)
Wed, Nov 30 PM 
14:45 - 15:35
(38) 14:45-15:10  
(39) 15:10-15:35  
Wed, Nov 30 PM 
15:50 - 17:30
(40)
RECONF
15:50-16:15 Design and Trial Production of Stochastic Resonance Processor using Differential Input Buffer in FPGA VLD2022-49 ICD2022-66 DC2022-65 RECONF2022-72 Akihiko Tsukahara, Sung-Gwi Cho, Keita Tanaka, Akihiko Homma, Yoshinori Uchikawa (Tokyo Denki Univ.)
(41)
RECONF
16:15-16:40 VLD2022-50 ICD2022-67 DC2022-66 RECONF2022-73
(42)
RECONF
16:40-17:05 Evaluation of Model Quantization Method on Vitis-AI for Mitigating Adversarial Examples VLD2022-51 ICD2022-68 DC2022-67 RECONF2022-74 Yuta Fukuda, Kota Yoshida, Takeshi Fujino (Ritsumeikan Univ.)
(43)
RECONF
17:05-17:30 Implementation of stereo matching with Kria SOM toward precise field crop height measurement VLD2022-52 ICD2022-69 DC2022-68 RECONF2022-75 Ryo Nakagawa, Yoshiki Yamaguchi (Univ. of Tsukuba), Iman Firmansyah (BRIN)
Wed, Nov 30 PM 
16:15 - 17:30
(44)
VLD
16:15-16:40 FPGA Implementation of Learned Image Compression VLD2022-53 ICD2022-70 DC2022-69 RECONF2022-76 Heming Sun (Waseda U), Qingyang Yi (UTokyo), Jiro Katto (Waseda U), Masahiro Fujita (UTokyo)
(45)
VLD
16:40-17:05 NA VLD2022-54 ICD2022-71 DC2022-70 RECONF2022-77 Kota Hisafuru, Nozomu Togawa (Waseda Univ.)
(46)
VLD
17:05-17:30 Error detection and countermeasures for computers inserted with hardware Trojan VLD2022-55 ICD2022-72 DC2022-71 RECONF2022-78 Takuro Kasai, Masashi Imai (Hirosaki Univ.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Masashi IMAI (Hirosaki Univ. )
E-: bi-u 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
ICD Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
Contact Address Koji Nii (TSMC Design Technology Japan)
E-: ig 
DC Technical Committee on Dependable Computing (DC)   [Latest Schedule]
Contact Address Masayuki Arai (College of Industrial Technology, Nihon Univ.)
E-: ain-u 
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Chair: Kentaro Sano (RIKEN) 
Announcement RECONF website
http://www.ieice.org/~reconf/
RECONF slack
https://join.slack.com/t/reconfworkspace/shared_invite/zt-v3qeynk3-RsInu4wdjqU2t_ysqWvagg
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Kazushi Kawamura (Tokyo Inst. of Tech.)
E-: arciir 
Announcement Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/


Last modified: 2022-11-25 18:31:30


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