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| Presentation | 2023-01-20 13:45 Design and Implementation of Power Consumption Reduction Binary Neural Networks Using Adiabatic Quantum-Flux-Parametron Logic Tomoharu Yamauchi, Hao San (Tokyo City Univ.), Nobuyuki Yoshikawa (Yokohama National Univ.), Olivia Chen (Tokyo City Univ.)  SCE2022-14 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient，high performance information processing systems．It is a low power dissipation circuits in superconducting digital circuits．In this paper，we introduce an AQFP based binary neural network (BNN) design methodology utilizing an in-memory computing scheme，analog accumulation，and a crossbar structure．The proposed design can effectively resolve the memory issue in superconducting digital circuits by significantly reducing memory usage in a non-Von Neumann fashion compared to conventional neural networks．As a proof of concept，we designed and implemented an 8 × 8 AQFP BNN using the proposed design methodology targeting the AIST 10kA/cm2 4-layer niobium process．The Josephson junction count and energy dissipation of the proposed 8 × 8 BNN design are 2236 and 11.18 aJ，respectively | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | adiabatic logic / superconducting digital circuits / AQFP / binary neural networ / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 122, no. 347, SCE2022-14, pp. 6-11, Jan. 2023. | |
| Paper # | SCE2022-14 | |
| Date of Issue | 2023-01-13 (SCE) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SCE2022-14 |
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| Conference Information | |
| Committee | SCE |
| Conference Date | 2023-01-20 - 2023-01-20 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Superconducting Electronics |
| Paper Information | |
| Registration To | SCE |
| Conference Code | 2023-01-SCE |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Implementation of Power Consumption Reduction Binary Neural Networks Using Adiabatic Quantum-Flux-Parametron Logic |
| Sub Title (in English) | |
| Keyword(1) | adiabatic logic |
| Keyword(2) | superconducting digital circuits |
| Keyword(3) | AQFP |
| Keyword(4) | binary neural networ |
| Keyword(5) | |
| Keyword(6) | |
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| Keyword(8) | |
| 1st Author's Name | Tomoharu Yamauchi |
| 1st Author's Affiliation | Tokyo City University (Tokyo City Univ.) |
| 2nd Author's Name | Hao San |
| 2nd Author's Affiliation | Tokyo City University (Tokyo City Univ.) |
| 3rd Author's Name | Nobuyuki Yoshikawa |
| 3rd Author's Affiliation | Yokohama National University (Yokohama National Univ.) |
| 4th Author's Name | Olivia Chen |
| 4th Author's Affiliation | Tokyo City University (Tokyo City Univ.) |
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| Speaker | Author-1 |
| Date Time | 2023-01-20 13:45:00 |
| Presentation Time | 25 minutes |
| Registration for | SCE |
| Paper # | SCE2022-14 |
| Volume (vol) | vol.122 |
| Number (no) | no.347 |
| Page | pp.6-11 |
| #Pages | 6 |
| Date of Issue | 2023-01-13 (SCE) |
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