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| Paper Abstract and Keywords | ||
| Presentation | 2023-03-01 13:25 Programmable Binary Hyperdimensional Computing Accelerator for Low Power Devices Yuya Isaka (NAIST), Nau Sakaguchi (SJSU), Michiko Inoue (NAIST), Michihiro Shintani (KIT)  VLD2022-76 HWS2022-47 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Hyperdimensional computing (HDC) can perform various cognitive tasks efficiently by mapping data to hyperdimensional vectors consisting of thousands to tens of thousands of dimensions. On the other hand, since the main operations of HDC, Bind, Permutation and Bound, require several cycles in the computing unit, it is not necessarily efficient to perform HDC on CPU platform. In this paper, we propose a programmable accelerator specialized for HDC. Our accelerator can execute various tasks at high speed and with low power consumption by cooperating with the CPU. Furthermore, by making it possible to freely select three operations per cycle, our accelerator enables to support any HDC encoding method. Through evaluation experiments with the ARM-v7 processor, we show that the above operations can be accelerated by a maximum of 169 times. We also confirmed that our accelerator can improve the energy-delay product up to 13,469 times in the training of handwritten character recognition task. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Hyperdimensional Computing / Hardware accelerator / Domain-specific architecture / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 122, no. 402, VLD2022-76, pp. 19-24, March 2023. | |
| Paper # | VLD2022-76 | |
| Date of Issue | 2023-02-22 (VLD, HWS) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2022-76 HWS2022-47 |
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| Conference Information | |
| Committee | HWS VLD |
| Conference Date | 2023-03-01 - 2023-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2023-03-HWS-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Programmable Binary Hyperdimensional Computing Accelerator for Low Power Devices |
| Sub Title (in English) | |
| Keyword(1) | Hyperdimensional Computing |
| Keyword(2) | Hardware accelerator |
| Keyword(3) | Domain-specific architecture |
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| 1st Author's Name | Yuya Isaka |
| 1st Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 2nd Author's Name | Nau Sakaguchi |
| 2nd Author's Affiliation | San Jose State University (SJSU) |
| 3rd Author's Name | Michiko Inoue |
| 3rd Author's Affiliation | Nara Institute of Science and Technology (NAIST) |
| 4th Author's Name | Michihiro Shintani |
| 4th Author's Affiliation | Kyoto Institute of Technology (KIT) |
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| Speaker | Author-1 |
| Date Time | 2023-03-01 13:25:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2022-76, HWS2022-47 |
| Volume (vol) | vol.122 |
| Number (no) | no.402(VLD), no.403(HWS) |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2023-02-22 (VLD, HWS) |
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