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| Presentation | 2023-03-02 09:55 Implementation of power-outage tolerant VLSI system using asynchronous circuits Masashi Imai (Hirosaki Univ.)  VLD2022-86 HWS2022-57 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Re-initialization free systems which contain nonvolatile memory have been proposed in order to cope with power-outage. However, their implementation requires high costs. This paper describes a system that automatically saves only the minimum necessary data to always-on storage elements which are served by a separately prepared coin-cell battery when a power failure is detected. The stored data are saved until the external power supply is restored. Since it is not possible to assume when a power loss will occur, it is implemented using asynchronous circuits. In this paper, the design results using Rohm 0.18um process technology through the chip prototyping service of the University of Tokyo D.Lab are also introduced. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Asynchronous Circuits / Nonvolatile Memory / ASIC Chip Prototyping / Power-outage Tolerant VLSI / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 122, no. 402, VLD2022-86, pp. 79-84, March 2023. | |
| Paper # | VLD2022-86 | |
| Date of Issue | 2023-02-22 (VLD, HWS) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2022-86 HWS2022-57 |
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| Conference Information | |
| Committee | HWS VLD |
| Conference Date | 2023-03-01 - 2023-03-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2023-03-HWS-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of power-outage tolerant VLSI system using asynchronous circuits |
| Sub Title (in English) | |
| Keyword(1) | Asynchronous Circuits |
| Keyword(2) | Nonvolatile Memory |
| Keyword(3) | ASIC Chip Prototyping |
| Keyword(4) | Power-outage Tolerant VLSI |
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| 1st Author's Name | Masashi Imai |
| 1st Author's Affiliation | Hirosaki University (Hirosaki Univ.) |
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| Speaker | Author-1 |
| Date Time | 2023-03-02 09:55:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2022-86, HWS2022-57 |
| Volume (vol) | vol.122 |
| Number (no) | no.402(VLD), no.403(HWS) |
| Page | pp.79-84 |
| #Pages | 6 |
| Date of Issue | 2023-02-22 (VLD, HWS) |
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